VHDL code for half subtractor using behavioral method

Next up in this VHDL course, we will be writing the VHDL code for half subtractor using the behavioral architecture. First, we will understand the working of a half subtractor and then take a look at its truth table. We will then take a look at the syntax for the half subtractor’s VHDL programming. For the full code, scroll down.

Contents

Explanation of the VHDL code for half subtractor using behavioral method. How does the code work?

A half subtractor is an arithmetic combinational logic circuit that subtracts two bits and gives two outputs, the Difference, and the Borrow output. The half subtractor does not account the borrow’s value in the subtraction process, so it doesn’t exactly perform the entire subtraction. Hence it is known as the half-subtractor.

Logic circuit of the half subtractor

A half subtractor has two inputs and two outputs. As we know, the entity part of a VHDL program deals with declaring only the I/O ports of the logic circuit. Hence, that’s all the information we needed from this diagram of the half subtractor. The behavior of the half subtractor for writing its VHDL program is extracted from its truth table.

Truth table of the half subtractor

A	B	DIFFERENCE	BORROW
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

We are working with the truth table in the behavioral architecture of the half subtractors code. Hence, we will declare the I/O ports as vector quantities in the entity-architecture declaration. Let’s name the entity as HALFSUBTRACTOR_BEHAVIORAL_SOURCE.

The half-subtractor has two inputs and two outputs. Thus the vectors will have a size of two (1 downto 0). Moreover, since we are using behavioral architecture, keep in mind that we will be using two begin statements and a process statement between them.

entity HALFSUBTRACTOR_BEHAVIORAL_SOURCE is

    Port ( A : in  STD_LOGIC_VECTOR (1 downto 0);

           Y : out  STD_LOGIC_VECTOR (1 downto 0));

end HALFSUBTRACTOR_BEHAVIORAL_SOURCE;




architecture Behavioral of HALFSUBTRACTOR_BEHAVIORAL_SOURCE is


begin


process(A)


begin

One of the statement types offered to us by the behavioral architecture are the if-else-if statements. We saw syntax for these in our post on behavioral architecture. In this particular scenario, we will use our understanding of the behavior of the half-subtractor from its truth table and code it in using the if-else-if statements.

if (A = "00" or A = "11") then

Y<="00";

else if (A = "01") then

Y<="11";

else

Y<="10";

Don’t forget to close off the if statements and the process statement with their respective commands.

Full VHDL code for half subtractor using behavioral method

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;




entity HALFSUBTRACTOR_BEHAVIORAL_SOURCE is

    Port ( A : in  STD_LOGIC_VECTOR (1 downto 0);

           Y : out  STD_LOGIC_VECTOR (1 downto 0));

end HALFSUBTRACTOR_BEHAVIORAL_SOURCE;




architecture Behavioral of HALFSUBTRACTOR_BEHAVIORAL_SOURCE is


begin


process(A)


begin


if (A = "00" or A = "11") then

Y<="00";

else if (A = "01") then

Y<="11";

else

Y<="10";


end if;

end if;

end process;

end Behavioral;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity half_sub_tb is
end entity;

architecture tb of half_sub_tb is
component HALFSUBTRACTOR_BEHAVIORAL_SOURCE is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (1 downto 0));
end component;

signal A,Y : STD_LOGIC_VECTOR (1 downto 0);

begin

uut: HALFSUBTRACTOR_BEHAVIORAL_SOURCE port map(
A => A, Y => Y);

stim: process
begin
A <= "00";
wait for 20 ns;

A <= "01";
wait for 20 ns;

A <= "10";
wait for 20 ns;

A <= "11";
wait for 20 ns;
wait;

end process;

end tb;