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# VHDL code for an encoder using behavioral method – full code and explanation

In this post, we will take a look at implementing the VHDL code for an encoder using the behavioral method. First, we will take a look at the logic diagram and the truth table of the encoder and then the syntax. For the full code, scroll down.

Contents

## Explanation of the VHDL code for an encoder using behavioral method. How does the code work?

Encoding means to code some data. A digital encoder takes some data as input and converts it into code. That’s the principle of it. But how? When you have a 2-bit data, you can write it in four ways. 00, 01, 10, and 11. This means that 2-bit data is capable of storing four different types of data.

In a 4:2 encoder, the circuit takes in 4 bits of data as input. It then codes the data to give an output of two bits. Here, we will be writing the VHDL code for a 4:2 encoder using the behavioral modeling style of architecture.

When we talk about the behavioral model, we don’t need the circuit or the logic equation. All we need is data about the behavior of the circuit.

But what do we mean by behavior? By behavior, we mean, the response or output of a circuit under the application of a certain set of inputs. Does that create a picture in your mind?

If it does, it must look a lot like a truth table. And that’s correct. We need the truth table.

### Truth table of a 4:2 encoder

 A B C D Y0 Y1 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1

The approach of using case statements for the behavioral code of the encoder is very similar to how we wrote the VHDL code for the decoder using the behavioral model. The only thing that is probably changing between the two programs is the change in the number of I/O ports.

Let’s start with what we know to be the most essential part of every VHDL code. The entity-architecture pair. The entity will have the port declaration statements of four input ports and two output ports. For the sake of ease, we will define them in `STD_LOGIC_VECTOR` datatype.

```library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ENCODER_SOURCE is

Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);

Y : out STD_LOGIC_VECTOR (1 downto 0));

end ENCODER_SOURCE;

```

The behavioral code always has a `process` statement. The sensitivity list variable here would be the input vector `I`. We begin the architecture first, define the process, and then begin the process. This order is imperative.

```architecture Behavioral of ENCODER_SOURCE is

begin

process (I)

begin
```

The `if` sequential statement that we use in VHDL is not to be confused with the if or else-if statement that we are accustomed to in the C programming language. The syntax is a bit different here.

```if I = "0001" then Y <= "00";

elsif I = "0010" then Y <= "01";

elsif I = "0100" then Y <= "10";

else Y <= "11";
```

Towards the end, you need to close the begin statements, as well as the `if` statement.

```end if;

end process;

end Behavioral;```

## Full VHDL code for an encoder using behavioral method

```library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ENCODER_SOURCE is

Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);

Y : out STD_LOGIC_VECTOR (1 downto 0));

end ENCODER_SOURCE;

architecture Behavioral of ENCODER_SOURCE is

begin

process (I)

begin

if I = "0001" then Y <= "00";

elsif I = "0010" then Y <= "01";

elsif I = "0100" then Y <= "10";

else Y <= "11";

end if;

end process;

end Behavioral;```

## Testbench

```library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encoder_tb is
end entity;

architecture tb of encoder_tb is
component ENCODER_SOURCE is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (1 downto 0));
end component;

signal I: STD_LOGIC_VECTOR(3 downto 0);
signal Y: STD_LOGIC_VECTOR(1 downto 0);

begin

uut: ENCODER_SOURCE port map(
I => I, Y => Y);

stim: process
begin

I <= "0001";
wait for 20 ns;

I <= "0010";
wait for 20 ns;

I <= "0100";
wait for 20 ns;

I <= "1000";
wait for 20 ns;
wait;

end process;

end tb;```

## RTL schematic

As always, if you have any queries, we would love to address them. Just drop in a comment in the comments section below.

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