In this post, we will take a look at implementing the VHDL code for half adder & full adder using dataflow architecture. First, we will take a look at the logic equations of the circuits and then the syntax for the VHDL programming. For the full code, scroll down.

**Explanation of the VHDL code for half adder & full adder**** using dataflow method****. How does the code work?**

In the dataflow architecture approach, we can either use the logic equations of a circuit or its truth table to write the code using VHDL. We will be coding the circuits of the half adder and the full adder using the former option first. We will also write the VHDL code for the full adder with the dataflow architecture using its truth tables later in this post.

**Logic equation and logic circuit of a half adder**

A half adder is an arithmetic combinational circuit that takes in two binary digits and adds them. The half adder gives out two outputs, the SUM of the operation and the CARRY generated in the operation. Since this carry is not added to the final answer, the addition process is somewhat incomplete. Hence, it’s known as the *half *adder.

Below you will find the logic circuit and the corresponding logic equation of the half adder. This circuit is made using simple digital logic gates; the EX-OR and AND gates. We will use this equation to program a half adder circuit using VHDL.

SUM =

CARRY = AB

**Logic equation and logic circuit of a full adder**

A full adder, unlike the half adder, has a carry input. And thus, since it performs the full addition, it is known as a full adder. Accordingly, the full adder has three inputs and two outputs. The relation between the inputs and the outputs is described by the logic equations given below. We will use these equations for the VHDL program.

SUM =

CARRY = Y(A+B) + AB

We will begin writing the code by first declaring the entity-architecture pair. As we have seen in our previous posts, the entity-architecture pair completes two main objectives of a VHDL program.

- The entity declares all the input, output, or bi-directional ports and assigns their datatype as scalar or vector. Basically, the entity describes the external part of a logic circuit.
- The architecture defines the relations between these entity items. And there are three types (Dataflow, Behavioral, and Structural).

The syntax for the entity-architecture pair declaration for our program is as follows. The entity name that we have chosen is `ADDERS_SOURCE`

.

entity ADDERS_SOURCE is Port ( A,B,C : in STD_LOGIC; SUM : out STD_LOGIC_VECTOR (2 downto 0); CARRY : out STD_LOGIC_VECTOR (2 downto 0)); end ADDERS_SOURCE; architecture dataflow of ADDERS_SOURCE is begin

Once we have the `begin`

statement, we can use the powers given to us by the dataflow architecture and start assigning the ports using logic equations. To do this, we use the assignment operator, as shown below. For the half adder:

SUM(1) <= A xor B; CARRY(1) <= A and B;

and for the full adder full-adder:

SUM(0) <= A xor B xor C; CARRY(0) <= (A and B) or (B and C) or (A and C);

**VHDL code for half adder & full adder using dataflow method**

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ADDERS_SOURCE is Port ( A,B,C : in STD_LOGIC; SUM : out STD_LOGIC_VECTOR (1 downto 0); CARRY : out STD_LOGIC_VECTOR (1 downto 0)); end ADDERS_SOURCE; architecture dataflow of ADDERS_SOURCE is begin ---half-adder SUM(1) <= A xor B; CARRY(1) <= A and B; ---full-adder SUM(0) <= A xor B xor C; CARRY(0) <= (A and B) or (B and C) or (A and C); end dataflow;

Always remember to end the architecture.

**Explanation of the VHDL code for full adder**** using its truth table and the dataflow method****. How does the code work?**

Next, we will use another feature given to us by the dataflow architecture. We will use a circuits truth table to design it using VHDL.

### Truth** table for a full adder**

A |
B |
Y |
SUM |
CARRY |

0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 1 | 0 |

0 | 1 | 0 | 1 | 0 |

0 | 1 | 1 | 0 | 1 |

1 | 0 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 1 |

1 | 1 | 0 | 0 | 1 |

1 | 1 | 1 | 1 | 1 |

The entity-architecture declaration for the VHDL code of a full adder will have only one difference. We will declare the entities as vectors.

But why? Why not declare each input/output separately?

The reason is that since we are using the truth table of the full adder, we have three inputs and two outputs. We can easily assign two vectors, one to inputs and one to outputs. The input vector will have three slots. And the output vectors will have two slots. The first one will be the SUM, and the second one will be the CARRY. And generally speaking, when we are dealing with multiple inputs of the same kind, using vectors saves us a lot of complexity. Entity name: `FULLADDER_VIATRUTHTABLE`

.

entity FULLADDER_VIATRUTHTABLE is Port ( A : in STD_LOGIC_VECTOR (2 downto 0); O : out STD_LOGIC_VECTOR (1 downto 0)); end FULLADDER_VIATRUTHTABLE; architecture dataflow of FULLADDER_VIATRUTHTABLE is begin

Dataflow architecture has when-else statements that are very handy when coding with truth tables. We saw the syntax for the when-else statements in our post on the dataflow architecture. So using that syntax, we will assign the inputs to the output vector as follows:

O <= "00" when A = "000" else "10" when A = "001" else "10" when A = "010" else "10" when A = "100" else "11" when A = "111" else "01";

**VHDL code for full adder using dataflow method – via truth table**

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FULLADDER_VIATRUTHTABLE is Port ( A : in STD_LOGIC_VECTOR (2 downto 0); O : out STD_LOGIC_VECTOR (1 downto 0)); end FULLADDER_VIATRUTHTABLE; architecture dataflow of FULLADDER_VIATRUTHTABLE is begin O <= "00" when A = "000" else "10" when A = "001" else "10" when A = "010" else "10" when A = "100" else "11" when A = "111" else "01"; end dataflow;