View Course Path

VHDL code for EXOR using NAND & structural method – full code & explanation

In this post, we are coding the EXOR gate using NAND logic in VHDL. We will use the structural architecture for this program. The task is very straightforward. We will use the NAND logic gates as components to build the main circuit of an EXOR logic gate.

If you would like to read more about these digital logic gates and how to construct all gates using NAND, click here. First, we will take a look at the structures of the gates and then the syntax. For the full code, scroll down.

VHDL code for EXOR using NAND - structural model architecture
EXOR using NAND logic circuit

As evident, the logic circuit of an EXOR using NAND employs 4 NAND gates, two inputs, and a solitary output. Remember these details.

Additionally, take a look at all the inputs to each of the gates. If you recall from our previous post on the VHDL code for a full adder using structural modeling. We will need that information to define the signals for the code.

Explanation of the VHDL code for EXOR using NAND & structural method. How does the code work?

In keeping with the workflow style of the structural modeling architecture, we will first define the components. Since only one component is used here, we can easily define it using the NAND logical function in VHDL. This type of program falls under the dataflow model of coding in VHDL. You can see the VHDL coding of all logic gates using the dataflow method here.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity NANDGATE is

    Port ( A,B : in  STD_LOGIC;

           Y : out  STD_LOGIC);

end NANDGATE;


architecture dataflow of NANDGATE is


begin


Y <= A NAND B;


end dataflow;

Then we can right away declare the entity-architecture pair for the VHDL code of the EXOR using structural modeling. Between the architecture declaration and the begin statement we will write:

  1. the component declaration of the NAND gate.
  2. Signal declaration (to be assigned to the individual component ports in the code)
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity EXOR is

      Port ( A1,B1 : in STD_LOGIC;

               C : out STD_LOGIC);

end EXOR;



architecture structural of EXOR is



component NANDGATE is

       Port ( A,B : in STD_LOGIC;

                Y : out STD_LOGIC);

end component;


signal S0,S1,S2,S3:STD_LOGIC;

And now we
begin

The next part is simple. Just write the component labels (U1-U5) and assign the appropriate signals to their ports using the PORT MAP statement.

U1:NANDGATE PORT MAP(A=>B1,B=>B1,Y=>S0);

U2:NANDGATE PORT MAP(A=>A1,B=>A1,Y=>S1);

U3:NANDGATE PORT MAP(A=>A1,B=>S0,Y=>S2);

U4:NANDGATE PORT MAP(A=>S1,B=>B1,Y=>S3);

U5:NANDGATE PORT MAP(A=>S2,B=>S3,Y=>C);



end structural;

VHDL code for EXOR using NAND & structural method

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;




entity NANDGATE is

    Port ( A,B : in  STD_LOGIC;

           Y : out  STD_LOGIC);

end NANDGATE;




architecture dataflow of NANDGATE is




begin




Y <= A NAND B;




end dataflow;




library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;




entity EXOR is

      Port ( A1,B1 : in STD_LOGIC;

               C : out STD_LOGIC);

end EXOR;




architecture structural of EXOR is




component NANDGATE is

       Port ( A,B : in STD_LOGIC;

                Y : out STD_LOGIC);

end component;




signal S0,S1,S2,S3:STD_LOGIC;




begin




U1:NANDGATE PORT MAP(A=>B1,B=>B1,Y=>S0);

U2:NANDGATE PORT MAP(A=>A1,B=>A1,Y=>S1);

U3:NANDGATE PORT MAP(A=>A1,B=>S0,Y=>S2);

U4:NANDGATE PORT MAP(A=>S1,B=>B1,Y=>S3);

U5:NANDGATE PORT MAP(A=>S2,B=>S3,Y=>C);




end structural;

 

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity exor_nand_tb is
end entity;

architecture tb of exor_nand_tb is
component EXOR is
Port ( A1,B1 : in STD_LOGIC;
C : out STD_LOGIC);
end component;

signal A1, B1, C: STD_LOGIC;

begin

uut: EXOR port map(
A1 => A1,
B1 => B1,
C => C);

stim: process
begin

A1 <= '0';
B1 <= '0';
wait for 20 ns;

A1 <= '0';
B1 <= '1';
wait for 20 ns;

A1 <= '1';
B1 <= '0';
wait for 20 ns;

A1 <= '1';
B1 <= '1';
wait for 20 ns;
wait;

end process;
end tb;

Simulation result

 

Exor-using-nand-waveform

RTL-schematic

Exor-using-nand-structural-RTL

As always, if you have any queries, we would love to address them. Just drop in a comment in the comments section below.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.

Top