Design For Testability (DFT) Course – VLSI

Course content

What is Design for Testability (DFT) in VLSI?

A simple and easy to understand introduction to the concept of Design for Testability in VLSI for chip design and manufacturing. Design for Testability is a technique that adds testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the IC chip.

Fault Modeling in Chip Design – VLSI (DFT)

Fault modeling is one of the core methodologies employed in DFT for chip design. In this method, we devise certain models of commonly occurring faults and use those to test chips and improve manufacturing defects. These models are called fault models. In this post, we will take a look a the most common types of fault models, what they mean in terms of the actual defects, and how they are used to improve the quality of a chip.

Test Generation Principles in DFT (VLSI)

Though fault modeling helps us locate faults, we need test generation to accurately pin-point faults at the gate level model. In this post, we’ll understand the need for test generation for better fault detection. We’ll study the truth table, analytical XOR, & path sensitization methods.

Fault Collapsing methods and Checkpoint Theorem in DFT (VLSI)

Now that we have studied the generation of test patterns for checking for faults, and also fault modeling, it’s time to optimize. A large number of test patterns means more time spent testing. Ideally, we wish to test a chip in the least possible time with the maximum coverage of faults. To do this, we have some methods collectively known as fault collapsing or reduction. This post is an in-depth study of different fault collapsing methods in DFT (VLSI) like fault reduction using fault equivalence and fault dominance. We also have a couple of solved examples to help you get the hang of it.

Internal Scan Chain – Structured techniques in DFT (VLSI)

Scan is a structured DFT method that allows us to apply conventional ATPG test patterns to sequential circuits with the help of a special flip-flop element known as the scan flip-flop. In this post, we will learn all about this method with a couple of examples to help drive the concept home.

Introduction to JTAG Boundary Scan – Structured techniques in DFT (VLSI)

Boundary scan is a structured testing technique implemented in chips as part of improving the Design For Testability. JTAG is an industry-standard for implementing the boundary scan architecture. In this post, we will learn everything about the JTAG boundary scan architecture right down to the gate level.

More details

New posts are still being added to this course. 

What will you learn in this course?

  • Various types of faults
  • Test Pattern Generation
  • Boundary Scan
  • JTAG
  • MBIST

Are there any software or hardware requirements for this course?

 


What is the target of this course?

This course is part of our track in VLSI. We have designed these tracks and their constituent courses (like this one) to equip learners with the basic requirements of entry-level jobs or internships in the respective fields. Head over to the pages of any of these tracks to get more information.


Are there any pre-requisites for this course?


How many quizzes are there in this course?

One


I would like to suggest some topics to be covered, how can I do that?

You can visit the contact page linked in the footer of this webpage. Just select “Suggest Topics” from the subject dropdown menu of the form, mention the course and why you think your suggestion makes sense to be part of the curriculum.

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