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VHDL code for decoder using behavioral method – full code and explanation

Now that we have written the VHDL code for a decoder using the dataflow method, we will take up the task of writing the VHDL code for a decoder using the behavioral modeling architecture. First, we will take a look at the logic circuit of the decoder. Then we will take a look at its truth table to understand its behavior. And then, we will understand the syntax. For the full code, scroll down.

2:4 Decoder using gates
2:4 Decoder

Explanation of the VHDL code for decoder using behavioral method. How does the code work?

A decoder is a combinational logic circuit that does the opposite job of an encoder. It takes in a coded binary input and decodes it to give a higher number of outputs. If, in a system, a stream of data is encoded using an encoder, there needs to be a decoder on the other end to decode that data.

We are using the behavioral modeling method for writing the VHDL code for a 2:4 decoder. Thus, we will be defining its behavior, which we do by using the truth table.

Truth table of 2:4 decoder

A B Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

There are a number of sequential statements that VHDL offers to us to ease our coding effort. Here, we will be using case statements to define the behavior of the truth table shown above.

The case statements that we use in the behavioral modeling style of VHDL are different in syntax to the switch-case statements that we have in C. However, they are similar in their purpose. Which is to say that these statements divide the truth table up into cases.

For every case, there is a set of inputs that assign the output port to a set of outputs. To make things easier, we will define the inputs and outputs as STD_LOGIC_VECTOR datatypes.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DECODER_SOURCE is

    Port ( I : in  STD_LOGIC_VECTOR (1 downto 0);

           Y : out STD_LOGIC_VECTOR (3 downto 0));

end DECODER_SOURCE;


architecture Behavioral of DECODER_SOURCE is

Remember that a behavioral model has a process statement. The process statement has its own begin command. In addition to the begin command of the architecture declaration.

begin


process (I)


begin

The input signal ‘I’ is in the sensitivity list of the process statement. Thus the case works on the I signal.

case I is

when I is xyz_std_logic_value => output <= is this std_logic_value. This is the syntax for the case statement. It’s a bit confusing. You need to practice it. Check it out in action below:

when "00" => Y <= "0001" ;

when "01" => Y <= "0010" ;

when "10" => Y <= "0100" ;

when others => Y <= "1000" ;

Again, remember to put in the end statements for the case statements, the architecture, and the process.

end case;

end process;

end Behavioral;

VHDL code for a decoder using the behavioral modeling architecture method

2:4 DECODER BEHAVIORAL MODELING

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DECODER_SOURCE is

    Port ( I : in  STD_LOGIC_VECTOR (1 downto 0);

           Y : out STD_LOGIC_VECTOR (3 downto 0));

end DECODER_SOURCE;


architecture Behavioral of DECODER_SOURCE is


begin


process (I)


begin


case I is

when "00" => Y <= "0001" ;

when "01" => Y <= "0010" ;

when "10" => Y <= "0100" ;

when others => Y <= "1000" ;


end case;

end process;

end Behavioral;

 

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder_tb is
end entity;

architecture tb of decoder_tb is
component DECODER_SOURCE is
Port ( I : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;

signal I: STD_LOGIC_VECTOR(1 downto 0);
signal Y: STD_LOGIC_VECTOR(3 downto 0);

begin

uut: DECODER_SOURCE port map(
I => I, Y => Y);

stim: process
begin

I <= "00";
wait for 20 ns;

I <= "01";
wait for 20 ns;

I <= "10";
wait for 20 ns;

I <= "11";
wait for 20 ns;
wait;

end process;

end tb;

Simulation result

Decoder-waveform

RTL schematic

Decoder-RTL

As always, if you have any queries, we would love to address them. Just drop in a comment in the comments section below.

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