VHDL code for demultiplexer using behavioral method

In this post, we will take a look at implementing the VHDL code for demultiplexer using behavioral architecture. First, we will take a look at the logic circuit of the 1:4 demultiplexer. Then we will understand its behavior using its truth table. And then, we will understand the syntax. For the full code, scroll down.

Contents

Explanation of the VHDL code for demultiplexer using behavioral architecture method. How does the code work?

A demultiplexer is a data distributor. It takes in a single data line and connects it with one of the several output lines it has. It does this depending on the value of the select inputs.

1_4 demultiplexer _ 1_4 demux using gates — 1:4 demux using gates

Truth table of 1:4 demux

I0	S0	S1	Y0	Y1	Y2	Y3
I	0	0	I	0	0	0
I	0	1	0	I	0	0
I	1	0	0	0	I	0
I	1	1	0	0	0	I

The structure of the program will be the same that we have seen numerous times in the behavioral modeled circuits of this VHDL course.

The entity declaration will declare all the ports of the demultiplexer. The architecture declaration will be followed by a begin statement, then a process statement and then finally one more begin statement. The first begin statement is for the architecture and the second one is for the process.

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DEMUX_SOURCE is

Port ( I : in  STD_LOGIC;

S : in STD_LOGIC_VECTOR (1 downto 0);

Y : out STD_LOGIC_VECTOR (3 downto 0));

end DEMUX_SOURCE;

architecture Behavioral of DEMUX_SOURCE is

begin

The process statement is unique to the behavioral modeling style. This is because a process by its definition defines the functionality using sequential statements like if, elsif, case, and loops. If you not familiar with these sequential statements you should consider refreshing your knowledge with this C programming course.

The signals mentioned in parenthesis next to the process statement are part of what’s known as the sensitivity list. The signals mentioned here are important to the process. Any time any event occurs concerning these signals, the process jumps into action and executes the sequential statements.

process (I, S)

begin

Here we will be using the if-elsif command that is possible with VHDL. This is similar to the if-else commands we saw in C. These commands put forth a condition and then allow us to define the output for that particular condition. It’s a nifty programming tool that you should familiarize with. It finds uses in the behavioral modeling style extensively.

Let’s see it in action. Peer carefully over the syntax. Students generally forget the then part of the if-elsif statements. Moreover, keep the truth table close. We are essentially coding in the functionality of each case in the truth table.

if (S <= "00") then

Y(0) <= I ;

elsif (S <= "01") then

Y(1) <= I ;

elsif (S <= "10") then

Y(2) <= I ;

else

Y(3) <= I ;

Remember that the if-elsif sequential commands need a closing statement. Additionally, so does the process statement and architecture as a whole. Mind you, however, that the process statement never really ends. It remains in a state of perpetual suspension until the sensitivity list is triggered again.

end if;

end process;

end Behavioral;

Full VHDL code for a demultiplexer using the behavioral modeling method

1:4 DEMUX BEHAVIORAL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DEMUX_SOURCE is

Port ( I : in  STD_LOGIC;

S : in STD_LOGIC_VECTOR (1 downto 0);

Y : out STD_LOGIC_VECTOR (3 downto 0));

end DEMUX_SOURCE;

architecture Behavioral of DEMUX_SOURCE is

begin

process (I, S)

begin

if (S <= "00") then

Y(0) <= I ;

elsif (S <= "01") then

Y(1) <= I ;

elsif (S <= "10") then

Y(2) <= I ;

else

Y(3) <= I ;

end if;

end process;

end Behavioral;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demux_tb is
end entity;

architecture tb of demux_tb is
component DEMUX_SOURCE is
Port( I : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;

signal I: STD_LOGIC;
signal S: STD_LOGIC_VECTOR (1 downto 0);
signal Y: STD_LOGIC_VECTOR (3 downto 0);

begin
uut: DEMUX_SOURCE port map(
I => I,
S => S,
Y => Y);

stim: process
begin
I <= '1';

S <= "00";
wait for 20 ns;

S <= "01";
wait for 20 ns;

S <= "10";
wait for 20 ns;

S <= "11";
wait for 20 ns;
wait;

end process;

end tb;