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# CMOS Inverter – The ultimate guide on its working and advantages

In the modern world, we are surrounded by digital electronics all around us. Most of these digital electronics are made using semiconductor devices. One of the major breakthroughs in the field of electronics was the introduction of CMOS technology. The term CMOS stands for “Complementary Metal Oxide Semiconductor,” this means that we use both NMOS and PMOS devices in order to achieve the desired digital logic.

In this post and the ones that follow, we will go through the transistor level implementation of CMOS technology. We will try to understand how each of the gates are formed using simple transistor devices. As we are concerned with CMOS technology, we will only be dealing with logic gate implementations using MOSFETs. For the design of gates, the factors a designer must have in mind are as follows:

• Speed: What is the maximum delay caused by the circuit. What are the speed limits?
• Power: How much power is drawn by the circuit while operating at a certain speed?
• Noise: How much noise in the input signal can the circuit handle without degrading the output signal?

We will try to answer these questions as we move forward with this CMOS course. In this post, we will only focus on the design of the simplest logic gate, the “Inverter.” We will try to understand the working of the CMOS Inverter, its Voltage Transfer Characteristics, and an important parameter called “Noise Margins.”

The exact detailed physics of the MOSFET device is quite complex. But even if we consider the simple ideal current-voltage relationships, we can conclude a lot about the working of the CMOS inverter.

Hence, before we begin this post, make sure that you are comfortable with the IV relation in different modes of operation for both NMOS and PMOS devices (Ideal IV characteristics as well as Non-ideal IV characteristics). Additionally, at some point, we will be considering some concepts for channel length modulation i.e., how the current still varies with drain-to-source voltage in the saturation region.

Contents

## Fundamental results on working of MOSFETs

In this section, we will discuss some of the results of a MOSFET, which will help us in the upcoming sections of the post. The results derived here assumes that the reader is aware of “Small Signal Analysis.” If that is not the case, then please go through some of the standard texts that discuss small-signal analysis in a generic manner.

### Small signal gain(gm) of MOSFET

We have seen the drain current for an NMOS in the saturation region of operation, is given by:

$I_{D} = \frac{\mu_{n} W C_{ox}}{2 L} [(V_{GS} - V_{T})^2] (1 + \lambda V_{DS})$.

$I_{D} = \frac{k_{n}}{2 } [(V_{GS} - V_{T})^2] (1 + \lambda V_{DS})$.

Now, suppose we want to see how much the drain current changes with an infinitesimal change of the gate-to-source voltage. For this, we differentiate our drain current($I_{D}$) w.r.t. the gate-to-source voltage($V_{GS}$). We term this derivative as the “Transconductance” or the “Small Signal Gain$g_{m}$ of the NMOS at the given biasing condition.

$g_{m} = \frac{d I_{DS}}{V_{GS}} = k_{n} (V_{GS} - V_{T}) (1 + \lambda V_{DS})$

Here, the quantities $I_{D}$ and $V_{GS}$ are the DC values of drain current and gate-to-source voltage respectively at the biasing point of the NMOS.

As an approximate value, we can neglect the effect of channel length modulation, and then we get:

$g_{m} = k_{n} (V_{GS} - V_{T})$

Some of the alternate forms of the equation are given by manipulating the current-voltage relations:

$g_{m}$  = $\frac{2 I_{DS}}{V_{GS} - V_{T}}$.

$g_{m}$ = $\sqrt{2 k_{n} I_{D}}$.

Thus, the simplest small-signal model of an NMOS device is shown in figure 1:

You can observe that we have placed a voltage-controlled current source between the drain and source terminal.

### Output resistance of the MOSFET

The MOSFET in its saturation region can be thought of as an ideal current source. The current through the MOSFET doesn’t depend on the voltage across it, which is $V_{DS}$. But considering channel length modulation, we see that the drain current does vary linearly with the drain-to-source voltage. This means that it acts as a non-ideal current source, with a resistance in parallel.

To take into account this effect, we find out the derivative of drain current $I_{D}$ w.r.t. the drain-to-source voltage $V_{DS}$:

$\frac{d I_{D}}{d V_{DS}} = \frac{k_{n}}{2 } [(V_{GS} - V_{T})^2] (\lambda)$.

Output conductance =  $g_{out} = \frac{k_{n}}{2 } [(V_{GS} - V_{T})^2] (\lambda)$.

Also we can approximate this to:

$\frac{d I_{D}}{d V_{DS}} = \lambda I_{D}$

Taking the inverse of this derivative gives us the small-signal resistance that is present between the source and drain terminal.

$r_{o} = [\frac{d I_{D}}{d V_{DS}}]^{-1} = \frac{1}{\lambda I_{D}}$

Thus, the final small-signal model we obtain for a MOSFET is shown in figure 2.

### Differences in PMOS and NMOS

Low side and High side switch

Before we begin, there is a subtle point to note about the NMOS and PMOS transistors.

The source for the NMOS transistor is generally connected to the lowest potential w.r.t. the drain or the body. Thus, if we connect the drain of the transistor to some other arbitrary circuit, by controlling the gate potential, we can pull down the drain connection to ground when we enter into the saturation region. Hence, the NMOS transistors are generally used as “pull-down” or “low-side” switch.

On the contrary, the source of the PMOS is generally connected to the highest most potential w.r.t. the drain or the body. In a similar manner, the PMOS transistor can be used to pull up any circuit node to the highest potential (supply potential) in the circuit. Thus the PMOS transistors are generally used as “pull-up” or “high-side” switch.

Mobility Considerations

One more thing to note is that the electron mobility is almost twice as that of the hole mobility. Hence we have:

$\mu_{p} = \frac{\mu_{n}}{2}$; keeping other parameters equal, we get:

$k_{p} = \frac{k_{n}}{2}$

Hence, if we have an NMOS and a PMOS of equal dimensions and both operating at the same voltages, then the current for the PMOS will be roughly half that of the NMOS. Moreover, the “on-conductance” of the PMOS will be half that of the NMOS.

In common practice, to obtain symmetrical operations in the circuit, the width (W) of the PMOS should be kept roughly twice of the NMOS. But due to some other non-ideal effects, it is not kept exactly to be twice. These will be discussed in detail once we start off with the formal derivations of input-output relation in a CMOS device.

## Working of CMOS inverter

In this section, we will see in detail the construction of the CMOS inverter. We will see it’s input-output relationship for different regions of operation.

### Circuit of a CMOS inverter

A detailed circuit diagram of a CMOS inverter is shown in figure 3. The different voltages are also marked in the diagram itself.

The body terminal of NMOS is connected to the ground (here denoted as $V_{SS}$) and that of the PMOS is connected to the supply voltage ($V_{DD}$). This is in order to eliminate the body effect as the source and body are connected together in both the transistors. Below, we figure out some of the voltage relation that will be useful in further calculations:

$V_{gsn}$ = gate-to-source voltage of NMOS = $V_{in}$.

$V_{dsn}$ = drain-to-source voltage of NMOS = $V_{out}$.

$V_{gsp}$ = gate-to-source voltage of PMOS =$V_{in}$$V_{dd}$.

$V_{dsp}$ =  drain-to-source voltage of PMOS = $V_{out}$$V_{dd}$.

A simplified notation of the CMOS inverter circuit generally used is shown in figure 4.

In this post, we will only be considering the static behavior of the inverter gate. This means that we don’t have any load resistance connected to the output terminal. The voltages are varying very slowly. Thus, the MOSFET parasitic capacitances can be neglected (open-circuited). This type of condition is called “Pseudo-Static.”

As there is no resistance, we can write: $I_{dn} = I_{dp}$.

The current flowing from supply line $V_{DD}$ to ground line $V_{SS}$ at any point of operation is called “Cross-over Current”. And this current is denoted by $I_{cr}$. We might also represent this current by $I_{d}$, and call it the drain current.

### Regions of operation

We divide the functioning of MOSFET over five regions of operation. These regions are discussed in detail below. For some of the cases, the calculations for the input-output relation become very lengthy. So, we will only discuss the equations and the method to obtain the final results. If interested, the readers can go through the calculations by themselves.

#### Operation Stage 1

Suppose we apply an input voltage such that:

$0 \leq V_{in} \leq V_{Tn}$

Then, we are sure that the NMOS transistor M1 is in the cut-off region. Therefore, the crossover current will be zero at this point of operation. The potential at the output terminal is equal to the supply voltage $V_{dd}$.

For the PMOS transistor M2, the source to gate voltage $V_{gsp}$ is definitely greater than $\mid V_{Tp} \mid$. This means M2 is not in the cut-off region. But the current flowing through it is zero. This can only be possible when M2 is in the linear region with $V_{dsp} =0$.

In the linear region, the conductivity of the PMOS transistor is given by:

$G_{lin,p} = k_{n}(- V_{gsp} + V_{Tp}) \approx k_{n}(V_{dd} + V_{Tp})$

On the other hand, the conductivity of NMOS transistor M1 is 0.

To summarise, $I_{d} = 0; V_{out} = V_{dd}$. The transistor M1 is in cut-off mode and the transistor M2 is in linear mode.

#### Operation Stage 2

As we keep on increasing the input voltage, we will cross the $V_{Tn}$. At this point, the NMOS transistor will come out of the cut-off region. As the output voltage was $V_{dd}$ (much greater than overdrive voltage) in the previous operating point, the NMOS transistor will enter into saturating.

For PMOS transistor, the $V_{sdp}$ is still very low and less than it’s override voltage. So the transistor M2 will continue to operate in it’s linear region. Hence, for the voltage range $V_{Tn} \leq V_{in} \leq V_{inv}$:

For NMOS, we can write:

$I_{dn}$ = $(\frac{k_{n}}{2})$(Vin – VTn)2

And, for the PMOS, we can write:

$I_{dp}$= $(\frac{k_{p}}{2})$[2(Vin – Vdd – VTp)(Vout – Vdd) – (Vout – Vdd)2]

The quantity $V_{inv}$ will be discussed in the section for operation stage 3. For now, assume it to be a value very close to $\frac{V_{dd}}{2}$.

As there is no resistive load attached to the output terminal, we can equate both the currents:

$I_{dp} = I_{dn}$ ; this gives us a quadratic in $(V_{out} - V_{dd})$.

The final solution from solving the above equation is:

$V_{out}$= (Vin – VTp) + $\sqrt{(V_{in} - V_{dd} - V_{Tp})^{2} - (\frac{k_{n}}{k_{p}})(V_{in} - V_{Tn})^{2}}$

The overall equation is very complex, but for our understanding we will just have to make some simple observations. We can observe from the equation that as we increase $V_{in}$ beyond $V_{Tn}$, the output voltage $V_{out}$ drops with slope becoming more negative. Putting $V_{in} = V_{Tn}$ in the equation gives back $V_{out} = V_{dd}$. This means that our equation is valid even at the edge of operation region 1.

#### Operation Stage 3

The previously mentioned voltage $V_{inv}$ is called the “Inverter Threshold” or the “Trip Point” of the CMOS inverter. We define this as the input voltage for which both the transistors are in saturation. As both of M1 and M2 are in the saturation region, we can write the currents as:

$I_{dn} = (\frac{k_{n}}{2}) (V_{in} - V_{Tn})^{2}$.

$I_{dp} = (\frac{k_{p}}{2}) (V_{dd} - V_{in} + V_{Tp})^{2}$.

Equating the currents, $I_{dp} = I_{dn}$; and solving for $V_{in}$ we get:

$V_{in} = \frac{V_{dd} + V_{Tp} + (\sqrt{\frac{K_{n}}{K_{p}}}) V_{Tn}}{1 + (\sqrt{\frac{K_{n}}{K_{p}}})}$

The “Inverter Threshold” is given by $V_{inv} = \frac{V_{dd} + V_{Tp} + (\sqrt{\frac{K_{n}}{K_{p}}}) V_{Tn}}{1 + (\sqrt{\frac{K_{n}}{K_{p}}})}$

As we can see from the above result that the equations give us an explicit value of input voltage. There is no dependance on the output voltage. This was due to the fact that the current through the transistors didn’t depend on the $V_{out}$. Essentially we have connected two ideal current sources in parallel.

The derivative of $V_{in}$ w.r.t. $V_{out}$ is zero. Taking the inverse of the derivative we get the slope of output voltage v/s input voltage curve at this point to be infinite. It means that the output voltage can change indefinitely for the input voltage $V_{in} = V_{inv}$. But wait, the transistors M1 and M2 should stay in the saturation region for that to happen. So the saturation condition puts a bound on the swing of output voltage when we are at the inverter threshold point. Thus, the range of $V_{out}$ is given by:

$V_{inv} - V_{Tn} \leq V_{out} \leq V_{inv} - V_{Tp}$

If we consider the channel length modulation effect, then the MOSFETs are no longer ideal current sources. There will also be a $V_{DS}$ dependence of the current. Thus, considering the output resistance we will get a finite slope of the transfer curve which will be discussed briefly in a later section on Shichman-Hodges Model.

#### Operation Stage 4

Now, if we increase the input voltage above $V_{inv}$, then the gate voltage increases. This means the overdrive voltage for NMOS increases and that for the PMOS decreases. Hence, the PMOS stays in the saturation region but the NMOS will enter into linear region. This is a situation opposite to that of in the case of operation stage 2.

For the range $V_{inv} \leq V_{in} \leq V_{dd} + V_{Tp}$; writing the equations for current and equating them, we get:

$V_{out}$ = (Vin – VTn) +$\sqrt{(V_{in} - V_{Tn})^{2} - (\frac{k_{p}}{k_{n}})(V_{in} - V_{dd} - V_{Tp})^{2}}$

If we put $V_{in} = V_{dd} + V_{Tp}$ i.e. at the edge of operation stage 4, we get:

$V_{out} = 0$

This means that we will have the output voltage = 0 after this point.

#### Operation Stage 5

For the voltage range $V_{dd} + V_{Tp} \leq V_{in} \leq V_{dd}$

The PMOS is in the cut-off region, therefore the conductance of transistor M2 will be zero. This region is opposite to operation stage 1. We have the NMOS out of cut-off, but the current is zero. It means that the NMOS is in linear region with $V_{dsn} = 0$. So the output point is essentially connected to ground.

$V_{out} = V_{ss} = 0$

And also the conductivity of the NMOS transistor is given by:

$G_{lin,n} \approx k_{n}$(Vin – VTn)

## Shichman-Hodges Model

Recall that while both the transistors were in the saturation region at the trip point of the inverter, the output voltage varied indefinitely. This was due to the fact that we assumed the MOSFETs to be ideal current sources which they are not. So, the Schishman-Hodges Model takes into account the output resistance of the MOSFETs. In this section, we will try to come up with a value of the slope at the trip point. We will see how the slope varies w.r.t. the channel length modulation coefficient $\lambda$.

As there is also an output resistance present in the circuit, the current will also depend on the drain-to-source voltages for both the transistors. The schematic in figure 5 shows the DC operating point of the transistor when $V_{in} = V_{inv}$ (inversion threshold value).

At this DC biasing point, we will perform small-signal analysis and come up with the gain of the input-output curve at this point. By shorting the large signals(as shown in figure 5 for $V_{DD}$), we get a small-signal equivalent of the circuit, as shown in figure 6.

As we are shorting out the supply and ground, the current sources are in parallel, and also the output resistances come in parallel.

So, the conductance will add up for the output resistance in parallel. And as the small-signal gate voltage applied to the MOSFETs are the same, the transconductances will also add up for the current sources. Note that in figure 5, we already considered that with a change in small-signal voltage, the currents in NMOS and PMOS would be in opposite directions. So, placing the current sources in parallel now results in the addition of the currents flowing through the current sources.

We can write the current through the circuit to be:

$I = (g_{m,n} + g_{m,p}) V_{in}$ , and we also have:

$- I = V_{out} (g_{out,p} + g_{out,n})$.

Substituting current in the above equation, we get:

$\frac{V_{out}}{V_{in}} = - \frac{g_{m,n} + g_{m,p}}{ g_{out,n} + g_{out,p}}$

This means that the gain offered by the circuit at the inversion threshold point is given by:

$\frac{d V_{out}}{d V_{in}} = - \frac{g_{m,n} + g_{m,p}}{ g_{out,n} + g_{out,p}}$

We replace the transconductance in the equation with:

$g_{m,p} = - k_{p} (V_{gsp} - V_{Tp})$;

$g_{m,n} = k_{n} (V_{gsn} - V_{Tn})$;

and output conductance terms in the equations are replaced by:

$g_{out,p} = (\frac{k_{p}}{2})$ ($V_{gsp} - V_{Tp})^{2}$ $\lambda_{p}$;

$g_{out,n} = (\frac{k_{n}}{2}) (V_{gsn} - V_{Tn})^{2} \lambda_{n}$;

We substitute the above values in the equation for slope and finally put $V_{in} = V_{dd}/2$. We assume that the two transistors are symmetric in terms of their $k, \lambda, V_{T}$ values. This gives us the result that:

Amplification = $\nu = \frac{-4}{\lambda (V_{dd} - 2 V_{T})}$;

Consider that we don’t have much control over the supply voltage and the threshold voltage. Then, we observe that there is only a $\lambda$ dependence for the inversion point amplification factor $\nu$. The channel length modulation coefficient $\lambda$ varies inversely with the channel length. From this we can conclude that the amplification $\nu$ will increase as we increase our channel length of both the transistors and vice versa.

Generally, we have a supply voltage $V_{dd}$ which is greater than $2V_{T} (\approx 1.2 V)$. But suppose, as we keep on decreasing supply voltage and bring it closer to the value $2 V_{T}$. Then this will result in the slope to increase till infinity. Physically, one can think of this as a situation where M2 enters cut-off as soon as the M1 comes out of cut-off. Though in practice, the transitions will be smooth due to subthreshold region conduction.

## Voltage Transfer Characteristics of CMOS

In this section, we will plot the output vs input curves that we obtained from solving the above equations. We will try to figure out the characteristics at different points of operation. Also we will plot the variation of cross-over current/drain current $I_{d}$ as we sweep the input voltage from 0 to $V_{dd}$. Finally we will discuss in brief the importance of this curve from a digital gate design point of view.

### Plot of output voltage vs input voltage

The “Voltage Transfer Characteristics” of the CMOS inverter is shown in figure 7. The different stages of operation of the CMOS as discussed in the mathematical derivation are also marked in the diagram.

As we can see that for $V_{in}$ less than $V_{Tn}$, the output voltage is $V_{dd}$. The CMOS is marked as operating in region 1. As we increase $V_{in}$ beyond $V_{Tn}$, we see that the output starts decreasing with the slope becoming more negative. This region is marked by 2. Then we reach the trip point, this is a singleton point and hence region marked by 3 only consists of one single point: $V_{in} = V_{inv}$. On increasing the voltage further, the output $V_{out}$ continues to fall but this time with the slope becoming less negative. This is marked as region 4. After $V_{in}$ becomes more than $V_{dd} + V_{Tp}$, we enter into region 5 and $V_{out}$ = 0.

The characteristics depend on what values of parameter we choose for the NMOS and PMOS transistors. We have seen in the derivation part that only if we choose $k_{n} = k_{p}$, then only we get  $V_{inv} = V_{dd}/2$. But suppose we have selected transistors such that $k_{n} > k_{p}$ and the threshold voltages are kept same. Then, the denominator will have a value more than 2. This will lead to $V_{inv}$ being less than $V_{dd}/2$. Then the whole VTC will shift to left. Similarly if we have $k_{n} < k_{p}$, then $V_{inv}$ will be greater than $V_{dd}/2$ and the whole VTC will shift to right.

### Crossover current (Drain current)

The plot in figure 8 shows the drain current $I_{d}$ variation w.r.t. the applied input voltage $V_{in}$. The current is zero when any one of the transistors is in cut-off. Therefore, $I_{d} = 0$ for both the region 1 and region 5.

The current reaches it’s peak at region 3 which is given by a singleton point $V_{in} = V_{inv}$. At this point, both the transistors are in saturation, hence we can calculate the $I_{max}$ to be:

$I_{max} = (\frac{k_n}{2}) (V_{in} - V_{Tn})^{2}$ ; one can also use the equation for PMOS

We know that at this point, $V_{in}$ is given by:

$V_{in} = V_{inv} = \frac{V_{dd} + V_{Tp} + (\sqrt{\frac{K_{n}}{K_{p}}}) V_{Tn}}{1 + (\sqrt{\frac{K_{n}}{K_{p}}})}$

Substituting this value in our previous equation, we get:

$I_{max} = (\frac{K_n}{2}) (\frac{V_{dd} + V_{Tp} - V_{Tn}}{1 + (\sqrt{\frac{K_{n}}{K_{p}}})})^{2}$

This $I_{max}$ is commonly referred to as “Peak Crossover Current”.

### Inverter use in Logic gates

The performance of a digital circuit is defined by its ability to discriminate between a “High-Level” input and a “Low-Level” input. Suppose we provide an input to the inverter, which is, say close to $V_{dd}$ value. The input signal is also generated by some previous stage logic circuit. Hence, due to error in the previous stages, the input to this inverter is a little lower than $V_{dd}$. We would ideally want the inverter to treat this input as a signal of value exactly $V_{dd}$.

Similarly, we can have an input signal value close to $V_{ss}$ or zero voltage, but a little bit more than zero. In this scenario also, we would want our inverter to treat it as if the input were exactly zero.

The same plot for voltage transfer characteristics is plotted in figure 9. But, this time, we have drawn the figure for an understanding of the CMOS inverter from a digital circuit application point of view. There are three regions in total defined by “Logic High,” “Logic Low,” and Undefined (X). This plot will be discussed in detail when we discuss the “Noise Margins” in the next section.

## Noise Margins

In the previous section, we have seen the voltage transfer characteristics of the CMOS inverter. The same plot is redrawn below for quick reference. In this section, we will analyze this curve in a detailed manner and arrive at certain conclusions from a digital circuit point of view.

For digital applications, we would like to use the CMOS inverter as a binary discriminator. This means that there will be two specific input voltages in the VTC, such that only between these two values, the inverter will amplify the signal. Outside the region defined by these two values, the inverter will attenuate the signal. These regions are marked in the plot shown in figure 10. The specific input voltages mentioned are denoted by $V_{il}$ and $V_{ih}$.

In mathematical terms, attenuation means that the absolute value of gain is less than 1. Similarly, amplification means that the absolute value of the gain is more than 1. As the curve is moving from the output voltage of $V_{dd}$ to 0, we expect that there will be two points where the slope of the curve will be -1. For certain ranges of input, we have the output being constant either equal to 0 or equal to $V_{dd}$. This means we are bound to have regions for which the slope of the curve more negative than -1, i.e., region of amplification.

The values for $V_{il}$ and $V_{ih}$ are obtained by equating the slope of the curves to be -1 in their respective regions.

The slopes can become -1 only in the regions 2 and 4. In this region, one of the transistors is in the linear region, and the other one is in the saturation region. For the ease of writing the final results, we define a quantity m as:

$m = \frac{\mu_{n} (W/L)_{n}}{ \mu_{p} (W/L)_{p}}$

Then finally, solving for the values of $V_{il}$ and $V_{ih}$, we get:

$V_{il} = \frac{2 \sqrt{m} (V_{dd} - V_{Tn} + V_{Tp})}{(m-1) \sqrt{m+3}}$$\frac{ V_{dd} - m V_{Tn} + V_{Tp}}{a-1}$ ;

$V_{ih} = \frac{2 m (V_{dd} - V_{Tn} + V_{Tp})}{(m-1) \sqrt{1+3m}}$$\frac{ V_{dd} - m V_{Tn} + V_{Tp}}{a-1}$ ;

Assuming the symmetric conditions, we get the values as:

$V_{il} = (3/8)V_{dd} + (1/4) V_{T}$ ,

$V_{ih} = (5/8)V_{dd} - (1/4)V_{T}$ ,

We define the “Noise Margins” for an inverter circuit as:

Noise Margin Low = $NM_{L} = V_{il}$

Noise Margin High = $NM_{H} = V_{dd} - V_{ih}$

In our symmetric case, we will have

$NM_{L} = NM_{H} = (3/8)V_{dd} + (1/4) V_{T}$

Note that the noise margins should be greater than $V_{T}$. This leads to the fact that all of our calculations are only valid in the case where $V_{dd} > 2 V_{T}$.

For a physical implication of noise margins, one can consider that we are operating at a point such that $V_{in} < V_{il}$. Then due to random noise in our instruments, there is also a noise signal riding over our DC value of $V_{in}$. As we are operating in the attenuation region, the noise signals will get damped by the inverter. Same analysis is also true for operating in the region where $V_{in} > V_{ih}$.

But, if we do the same analysis in the region where $V_{il} < V_{in} < V_{ih}$, then the noise signals riding over our DC input signal will get amplified which is undesired. Thus, we would like to design our circuits such that they have a good enough noise margin.

And hence the output signal for an input of $V_{in} < V_{il}$ is termed as “Logic-High” output. And output signal for an input of $V_{in} > V_{ih}$ is termed as “Logic-Low” output.

Before the introduction of CMOS technology, there were other logics that we used. Some of these previous technologies were RDL (Resistor Diode Logic), TTL (Transistor-Transistor Logic), ECL (Emitter Coupled Logic), NMOS (Implemented only using n-channel MOSFETs).

The CMOS technology had advantages that have made it stand out as compared to the other type of logic. Some of these advantages are mentioned below:

• Very low static power consumption
• Very small space is consumed by each logical function
• Can work with a wide range of supply voltage(3V – 15V)
• Low variation in performance with variation in temperature
• The complexity of logic gate design is reduced

Despite these advantages, the speed of TTL technology is much better than as compared to CMOS. CMOS causes more propagation delay, which is in order of 50 ns. Whereas the propagation delay for TTL is around 10 ns.

## Conclusion

In this post, we have gone through the working of the simplest logic gate, the inverter. We have seen its implementation using CMOS technology. The voltage transfer characteristics is discussed in detail, along with the analytical solution for the input-output relation. We are now also familiar with the concepts of noise margins and how the CMOS inverter can be used in a digital circuit. Finally, we discussed the advantages of CMOS technology over other technologies in brief.

In the next post, we will understand the concepts regarding delays in CMOS inverters. This will give us an understanding of the speed limitations of CMOS technology. We will also see how the speed of operation varies with the power consumption in the circuit.

## One thought on “CMOS Inverter – The ultimate guide on its working and advantages”

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