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# Propagation Delay in CMOS Inverters

In the previous post on CMOS inverter, we have seen in detail the working of a CMOS inverter circuit. We are also now familiar with the typical voltage transfer characteristics of a CMOS inverter. Finally, we have seen the calculations for a very important parameter of an inverter called noise margins. We are also familiar with the physical meaning of these noise margins.

In this post, we will continue forward with our study on the CMOS inverter with new parameters that one should always keep in mind while designing digital CMOS circuits. Recall that in the previous post, we discussed the noise margins as an important parameter from the digital design point of view. This noise margins defined the allowable discrepancy we can have in the input of the inverter. This was mainly focussed on the noise considerations of a digital circuit. In this post, we will focus on the parameters that define the speed of operation of a CMOS circuit.

Before we begin, the reader should be comfortable with the mathematical derivations that we have done in the previous chapter on CMOS inverter. Also, the typical voltage transfer characteristics should be very familiar by now. In the sections that follow, we will first define the propagation delay in a generic manner. Then, we will understand the propagation delay for CMOS inverters. Finally, we will see what causes these delays and what we can do to minimize them.

Contents

## Defining “Delay” in a circuit

Every circuit has some parasitic capacitance components associated with it. In the chapter for non-ideal effects in MOSFETs, we have discussed the parasitic capacitance present in the MOSFET device. These capacitance results in delaying the voltage change in the circuit. So we will get limitations in our speed of operation depending on how fast we can charge or discharge these capacitors.

To illustrate how the capacitances affect the output waveforms, we take some examples of waveforms. We will also define certain quantities such as “Propagation Delay” and “Transition Delay,” which will help us in quantifying the speed performance of our inverter.

### Propagation delay

Suppose that we have a CMOS inverter whose output is connected to some next stage circuits. To test the speed performance of our circuit, we apply a step voltage at the input, as shown in the schematic in figure 1. Note that in the schematic, we have represented the capacitance offered by the next stage by a load capacitance $C_{L}$.

In the plot of output voltage in figure 2, there are two time intervals marked by $t_{phl}$ and $t_{plh}$. Here, the “p” in the subscript stands for propagation delay. The “hl” stands for high-to-low, and “lh” stands for low-to-high. The inverters in the circuit are operating between two voltages. The output high voltage is given by $V_{OH}$, and the output low voltage is given by $V_{OL}$.

The propagation delay for high to low is given by $t_{phl}$ and is defined as the time required for the output to fall from $V_{OH}$ to $(V_{OH} + V_{OL})/2$. Similarly, the propagation delay for low to high is given by $t_{plh}$ and is defined as the time required for the output to rise from $V_{OL}$ to $(V_{OH} + V_{OL})/2$. Note that the threshold voltage value used to define the delay time is at the middle of the output voltage range. This definition fits with the CMOS inverter circuit as the trip point is very close to $V_{DD}/2$.

The propagation delay $t_{p}$ is then defined as the average of $t_{plh}$ and $t_{phl}$:

$t_{p} = \frac{t_{phl} + t_{plh}}{2}$

### Transition time

We consider a similar situation for defining another similar quantity called transition time. For this, we also consider a step input voltage, the corresponding output curve obtained is shown in figure 3.

In the plot of the output voltage, there are two time intervals marked as $t_{thl}$ and $t_{tlh}$. The “t” in the subscript stands here for transition and “hl”(“lh”) stands for high-to-low(low-to-high). The $t_{thl}$ is defined by the time taken by output signal to come down from 90% to 10% of the $(V_{OH} - V_{OL})$ value. Similarly, $t_{tlh}$ is the time taken by output to rise up from 10% to 90% of the $(V_{OH} - V_{OL})$ value.

In a similar manner the transition time is defined by taking the average of these two quantities:

$t_{t} = \frac{t_{thl} + t_{tlh}}{2}$

### Practical input signals

The input signals to our CMOS inverter in the previous discussions was taken as an exact step function. But, for practical scenarios the inverter will also be driven by the output signal of some other logic gate. This means that the input signal to the inverter we are studying will be more of a “ramp-signal” rather than a step signal. To illustrate the effect of such an input signal, we have plotted the input and output voltage curves in figure 4.

Observe from the figure that the output signal starts to climb up once when the input signal goes below the point $\frac{V_{OH} + V_{OL}}{2}$. Similarly, the output voltage starts to drop once the input goes below the point $\frac{V_{OH} + V_{OL}}{2}$. This ultimately results in the output low pulse to be delayed w.r.t. the input high pulse.

## “Rise-time” and “Fall-time”

In this section, we will derive the mathematical expressions for the propagation delay $t_{d}$ discussed earlier. First, we will go through an approximate derivation and then will do a formal derivation. But, before we begin with our mathematical derivations, there two important results that we will be using. These results are important when working with capacitive circuits in large signal domain. These are given by:

• The change in charge across a capacitor is given by the current flowing through it times the time interval over which we see the change in charge. This quantity is also equal to the capacitance times the change in voltage across the capacitor. Mathematically:
$I \Delta T = \Delta Q = C \Delta V$
Note that this formula is valid when we are looking at a very short interval of time $\Delta t$. But, if we want to obtain insights on the working of a capacitive circuit using this formula, then we will use the average current “<I>” instead of the instantaneous current “I” in the equation. For many cases, we will be able to deduce the dependence of delay on different parameters by solving this equation only.
• For a capacitor with an initial voltage across it as $V_{i}$ and if we know that the final steady-state value of the voltage across it is $V_{f}$. We can write the voltage across the capacitance as a function of time to be:
$V(t) =V_{f} + (V_{i} - V_{f})e^{- t/\tau}$

Here the quantity $\tau$ represents the time constant of the circuit. $\tau$ is given by the product of the capacitance and the resistance in series with it at the time of charging or discharging.

$\tau = R \times C$

### Approximate Calculation

In this section, we will do an approximate calculation to figure out the propagation delay of an CMOS inverter if we have a capacitive load $C_{L}$ attached to it. For this purpose, we apply an ideal rising edge input to the inverter. Hence, the inverter output was initially high and now it will fall down to low value. This calculation will give us the value of $t_{phl}$. In order to get the value for $t_{plh}$, we will extrapolate the result.

When we cross the rising edge, then the input to the circuit is $V_{in} = V_{dd}$. Thus, the PMOS transistor is obviously in cut off region, so the equivalent inverter circuit formed is shown in figure 5.

At the instant of switching, the drain-to-source voltage of NMOS is equal to $V_{out} = V_{dd}$. And also, the gate-to-source voltage for the NMOS is equal to $V_{in} = V_{dd}$. This means for the instant the transistor is operating in its saturation region. Thus the value of current supplied by the inverter is given by:

$I_{dn} = \frac{k_{n}}{2} [(V_{dd} - V_{Tn})^2]$

Then, as the load capacitor $C_{L}$ discharges, the drain-to-source voltage falls below $V_{dd} - V_{Tn}$. At this point, the NMOS is in linear region.

Our propagation delay is defined by the time in which output falls from $V_{dd}$ to $V_{dd}/2$. At the point where $V_{out} = V_{dd}/2$, we have the current in the NMOS to be:

$I_{dn} = \frac{k_{n}}{2} [2(V_{dd} - V_{Tn})(V_{dd}/2) - (V_{dd}/2)^{2}]$

Taking these two extreme values of the current, we calculate the average current as:

$I_{avg} = \frac{k_{n}}{4}[(7/4)V_{dd}^{2} - 3 V_{dd} V_{Tn} + V_{Tn}^{2}]$

We, will put this into the equation:

$I_{avg} \Delta t = C_{L} \Delta V$

Here, $\Delta V$ is given by $V_{dd} - V_{dd}/2 = V_{dd}/2 and \Delta t = t_{phl}$

Simplifying the above equations and solving for $t_{phl}$ gives us:

$t_{phl} = \frac{C_{L} \alpha_{n}}{V_{dd} k_{n}}$

Here, $\alpha_{n} = \frac{2}{\frac{7}{4} - \frac{3V_{Tn}}{V_{dd}} + (\frac{V_{Tn}}{V_{dd}})^{2}}$

Similarly, the results for $t_{plh}$ will depend on the parameters of the PMOS, because in this case the NMOS will be in cut-off. The equivalent circuit for a falling edge input is shown in figure 6.

The value obtained for propagation delay for low to high transition is given by:

$t_{plh} = \frac{C_{L} \alpha_{p}}{V_{dd} k_{p}}$

Here, $\alpha_{p}$ is also a similar quantity, it’s value can be obtained by replacing $V_{Tn}$ with $\mid V_{Tp} \mid$ in the equation for $\alpha_{n}$.

Therefore, the propagation delay of the circuit is given by the average:

$t_{d} = (\frac{C_{L}}{V_{dd}})(\frac{\alpha_{n}}{k_{n}} + \frac{\alpha_{p}}{k_{p}})/2$

### Inference from approximate calculation

• The propagation delays are inversely proportional to the $k_{n}$ and $k_{p}$ values. This means as the conductivity of the transistors in there “on-state” increase, the delay time decrease. This also makes sense intuitively, as the series resistance in the RC circuit decreases, the time constant also decreases. Thus, there is faster rate of charging and discharging.
• The value of $\alpha$ depends on the value of the threshold voltage and supply voltage. Consider that the $V_{Tn} \approx - V{Tp}$. If, we want to match the delay values for high-to-low and low-to-high transitions, then:
$\frac{t_{phl}}{ t_{plh}} = \frac{k_{p}}{ k_{n}}$

If we have $k_{p} = k_{n}$, then both the delay times are equal.

• The delay time is directly proportional to the load capacitance $C_{L}$. From a design point of view, the parasitic capacitances present in the CMOS inverter should be aimed to be kept at a minimum value.
• The delay time is inversely proportional to the supply voltage $V_{dd}$. Considering that the $\alpha$ factor is not a very strong function of $V_{dd}$, we can say that as $V_{dd}$ increases, the speed of operation also increases. But, for small devices, there is a upper bound to the supply voltage that can be used. Also, the increase in supply voltage results in more power dissipation which will be discussed in the next post.

### Accurate calculations

In this section, we will derive a much more accurate value for the delay time. We will only go over the calculations for the output transition from low level to high level. For this purpose we will consider two time intervals. From $(0,t_{1})$, the PMOS transistor is in saturation and for $(t_{1}, t_{2})$, it is operating in linear region.

We consider that the PMOS transistor stays in it’s saturation region for a relatively very short time $t_{1}$. If the transistor is in saturation, then it acts like a constant current source. The current is given by:

$I_{dp} = \frac{k_{p}}{2} [(V_{dd} - \mid V_{Tp}) \mid)^2]$

We put this value of the current in the equation:

$I \Delta t = \Delta Q = C \Delta V$

Here, $\Delta t = t_{1}$ and $\Delta V = \mid V_{Tp} \mid$

Simplifying the equations and solving for $t_{1}$, we get:

$t_{1} = \frac{2 \mid V_{Tp} \mid C_{L}}{k_{p} (V_{dd} - \mid V_{Tp} \mid)^2}$

Then, we will solve for the time $V_{out}$ takes to rise to $V_{dd}/2$ from the initial value of $\mid V_{Tp} \mid$. In this region the transistor is in saturation mode, thus the current is given by:

$I_{dp} = (k_{p}/2) [2(V_{dd} - \mid V_{Tp} \mid)(V_{dd} - V_{out}) - (V_{dd} - V_{out})^{2}]$

We put the value of $I_{dp}$ in the relation given by:

$I_{dp} = C_{L} \frac{d V_{out}}{d t}$

This gives us an differential equation which can be solved to find $V_{out}$ as a function of time “t”. We will not perform the calculations here, but the differential equation can be easily solved by the following observations:

$\frac{k_p}{2 C_{L}} dt = \frac{d V_{out}}{2(V_{dd} - \mid V_{Tp} \mid) (V_{dd} -V_{out}) - (V_{dd} -V_{out})^{2}}$

Suppose that $V_{dd} -V_{out}$ = u and $2(V_{dd} - \mid V_{Tp} \mid)$ = a, then the RHS of the above equation simplifies to:

RHS = $\frac{- du}{au - u^{2}}$

Solve the above equations for “t” running from $t_{1}$ to $t_{2}$. And the output voltage runs from $\mid V_{Tp} \mid$ to $V_{dd}/2$.

Simplifying, we get:

$t_{2} - t_{1} = \frac{C_{L}}{k_{p}(V_{dd} - \mid V_{Tp} \mid)} ln(3 - 4 \frac{\mid V_{Tp} \mid }{V_{dd}})$

Here, $t_{2} = t_{plh}$. We replace the value of $\frac{1}{k_{p}(V_{dd} - \mid V_{Tp} \mid)}$ with $R_{lin,p}$. The relation is not exact but this will give us an idea of the effect of “on-resistance” on the propagation delay.

Finally, we get:

$t_{plh} = R_{lin,p} C_{L} ( ln(3 - 4 \frac{\mid V_{Tp} \mid }{V_{dd}}) + \frac{2 \mid V_{Tp} \mid }{ V_{dd} - \mid V_{Tp} \mid})$

suppose that $V_{dd} = - 4 V_{Tp}$, then, putting these values in the above equation we get:

$t_{plh} = R_{lin,p} C_{L}(0.693 + 0.667) \approx 1.36 R_{lin,p} C_{L}$

The rise in output voltage when we apply a negative edge input is shown in figure 7. For $V_{out} < \mid V_{Tp} \mid$, the PMOS transistor is in saturation. This region is marked as linear region or “linear charging”. And for $V_{out} > \mid V_{Tp} \mid$, the PMOS enters triode mode, this is marked by sublinear region or “sublinear charging”.

The derivation for $t_{phl}$ is analogous to the one we did above. The result we get is given by:

$t_{phl} = R_{lin,n} C_{L} ( ln(3 - 4 \frac{V_{Tn} }{V_{dd}}) + \frac{2 V_{Tn}}{ V_{dd} - V_{Tn}})$

The fall in output voltage on the application of a rising edge input signal is shown in figure 8. Similar to the charging of capacitance, the discharging is also divided into two regions. For $V_{out} < V_{DD} - V_{Tn}$, the NMOS is in saturation and this is marked as linear discharge. And for $V_{out} > V_{DD} - V_{Tn}$, the NMOS is in triode mode and this region is marked as sublinear discharge.

The readers are advised to check that the inference is drawn in the case of approximate calculation also holds for the accurate calculations. Note that the “on-resistance” is inversely proportional to the $k_{n}$ or $k_{p}$ values.

If we plot the above delay values w.r.t. the threshold voltages, we observe that the propagation delays increase with the rise in the magnitude of threshold voltages. Therefore having low threshold voltage values improves the speed of operation of the circuit.

Note that the hand calculations done in this section are not exact. They don’t take into account the non-ideal effects of the MOSFETs. For the exact relationships, one should use the different circuit simulators available. But, the hand calculations do provide a good amount of design insights. We must only proceed with simulations when we have some quantitative idea about the output of the circuit.

## Factors affecting propagation delay in CMOS inverters

We have earlier discussed the dependence of the propagation delay on various factors. In this section, we will summarise them and also look over some of the consequences from a design point of view.

### Threshold Voltage

With the decrease in the value of threshold voltage, the propagation delay also decreases. Thus, for faster circuit operation, we would like to choose MOSFETs with very low threshold voltages. This is why we have seen that the body and source terminals are connected in both the NMOS and PMOS in order to remove the body effect.

### Width (W) of the MOSFETS

As we have seen that the propagation delay decreases as we increase the $k_{n}$ and $k_{p}$ values for NMOS and PMOS respectively. Thus, we would like to keep higher values of (W/L). Generally, the channel length (L) is kept equal for the devices in order to have a similar order of channel length modulation effect. Thus if we increase the channel width (W), we will get an improvement in the speed of operation.

But, this increase in width also results in an increase of the parasitic capacitance in the CMOS inverter. If this inverter is driving some next stage logic gate, then it will see a high capacitive load. This will ultimately result in the degradation in the speed of the overall circuit.

### Supply voltage

The propagation delay has an inverse relation with the supply voltage($V_{dd}$). Thus increasing the supply voltage will result in an increase in the speed of the inverter.

But, for small devices, there is an upper limit to the supply voltage that can be used in order to not damage the circuit. Also, an increase in supply voltage results in the dynamic power consumption to increase.

The parasitic capacitance present in the overall CMOS inverter circuit manifests as the capacitive load($C_{L}$). The parasitic capacitance from both the current stage inverter and the next stage inverter is a cause of this load capacitor($C_{L}$). Thus, for better speed, we must keep the parasitic capacitances as low as possible. This parasitic capacitance will be discussed in brief in the next section.

### Short channel effects

As we have seen in the previous that there are a lot of non-ideal effects in the MOSFET device. But, we have done all our calculations only considering ideal IV characteristics. One of the most important effects of propagation delay considerations is “velocity saturation.

We are now aware that channel length is kept minimum in order to increase the conductivity of the device. But, for short channel device, the saturation happens due to velocity saturation and not due to channel length modulation. Thus, the saturation current will be lower than that in long channel devices. Therefore, the propagation delay will be more.

### Maximum operating frequency

Supposed that after optimizing the values of the MOSFETs in the CMOS inverter, we achieve a minimum delay of $t_{min}$. Then the maximum frequency over which we can operate the inverter will be:

$f_{max} = \frac{1}{t_{min}}$

But, we generally operate our digital circuit around the range $f = \frac{f_{max}}{20}$

We have a lot of logic gates cascaded together, and each of these logic gates uses multiple CMOS inverters. Therefore the cumulative delay of the whole circuit is much more than $t_{min}$. So we operate at a frequency much lower than $f_{max}$.

## The capacitance of CMOS inverters

Till now, we have been representing the capacitive load offered by the next stage with a simple capacitive load ($C_{L}$). In this section, we will try to get an understanding of the components that make up this capacitive load.

It should be clear by now that the capacitive load is just a manifestation of the parasitic capacitance in the MOSFETs and the capacitive elements present in the wiring used to connect the devices together. The different capacitance that constitutes our final $C_{L}$ is shown in figure 9.

We consider a circuit of two CMOS inverters. There are a total of four transistors in the circuit, namely M1, M2, M3, M4. In the circuit schematic, the capacitive components shown are due to gate-to-drain capacitance ($C_{gd}$), drain-to-body capacitance($C_{db}$), wiring capacitance($C_{w}$) and finally input capacitance of the load inverter($C_{g}$).

The circuit shown in the figure is quite complex to be solved by hand. Thus, we will make some modifications to the model in order to get a simpler circuit. The load capacitance value that will be obtained from this simplified model will not be accurate but will still give us enough insights. One thing to note that the wiring capacitance that we have mentioned becomes an important parameter as we scale down our ICs.

The capacitors $C_{db}$, $C_{w}$ and $C_{g}$ are easy to analyse as one of there terminals is connected to constant value. We would like to shift the capacitors $C_{gd}$ such that finally, one of its terminals is connected to a constant voltage value.

Note that the voltage across the capacitor Cgd changes from +Vdd to -Vdd or the other way around when we switch the inverter. Therefore the magnitude of change in voltage is 2 Vdd. But for every other capacitor, the magnitude of change is Vdd.

So, we shift the gate-to-drain capacitance in the circuit and place them in parallel with $C_{w}$, as shown in figure 10. In order to take into account the change of voltage, the equivalent capacitance has a value twice as that of the original one. Therefore, the new value of gate-to-drain capacitors is $2 \times C_{gd}$.

Thus, our final expression for the load capacitance becomes:

$C_{L} = C_{g3} + C_{g4} + C_{db1} + C_{db2} + (2 C_{gd1} + 2 C_{gd2} + C_{w})$

## Conclusion

In this chapter, we have seen how the speed performance of a CMOS inverter is quantified. We derived the formulae that define the propagation delay in a CMOS inverter circuit. We also saw how different parameters in the circuit affect the propagation delay of a CMOS inverter. Keep in mind that the CMOS inverter forms the building blocks for different types of logic gates. Hence, the delay in an overall logic circuit will also depend upon the delay caused by the CMOS inverters used.

One of the points we mentioned earlier that the speed of operation increases with an increase in supply voltage. But, also an increase in supply voltage value will result in more dynamic power dissipation in the circuit. We haven’t discussed why this is the case. The next post in this CMOS course is aimed at understanding this kind of effects only. We will learn about the different types of power consumption in a CMOS inverter and the factors that influence it.

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