Now that we have understood the on-chip memory organization and RAM structure of 8051 let us look at how to interface additional external Program Memory and Data Memory to the microcontroller.
Why do we need external memory, though? The 8051 has on-chip RAM and ROM to store the temporary variables and the program code, respectively. Surely that should suffice?
Actually, no. The reason is that 8051 is capable of performing high-level, complex operations that require a large amount of memory space. For most normal small applications the on-chip memory is enough. But when you’re talking about industrial usage, we need a lot more. We can interface a maximum of 64KB of program and data memory with the 8051 microcontrollers.
In this post, we’re going to interface these external memory elements to 8051 in the spirit that they will be required for complex operations that require a lot of memory space. Let’s begin!
Chip select logic
What is Chip Select Logic?
The chip select logic is just a simple logic that is developed using additional circuitry to choose one chip from multiple chips. If we’re interfacing more than one chip (they may be program ROM chip or data ROM or even data RAM), each sharing the same address space range (say 0000H to FFFFH), and the address lines of the microcontroller has the address 5FFFH on it, which chip is this address referring to? The chip select logic enables the microcontroller to answer that question and understand which chip to select for the particular address required to be accessed by the user.
How does Chip Select Logic work?
The central processing unit (CPU) provides the address of the location from where the data is desired. This address is in the form of a mixture of address lines and some control lines. The decoding circuit is responsible for decoding this information and locating the required memory block based on these signals.
We are going to discuss Chip select logic in SRAM and ROM.
All memory chips have one or more than one pins called the Chip Select (CS) pins (aka Chip Enable (CE) pins). These pins are commonly active-low pins, and we have to activate it to access the chip it belongs to.
In connecting a memory chip to the CPU, note the following points:
- The data bus of the CPU is connected directly to the data pins of the memory chip.
- Control signals RD (read) and WR (memory write) from the CPU are connected to the OE (output enable) and WE (write enable) pins of the memory chip.
- In the case of the address buses, while the lower bits of the address from the CPU go directly to the memory chip address pins, the upper ones are used to activate the CS/CE pin of the memory chip via an additional decoding circuitry. The latter is known as Chip Select Logic.
The three different ways to generate chip select logic
- Simple logic gates
- The 74LS138 latch
- Programmable logic
Logic Gates decoder circuit
If the CS pin were active-high, we would have used, AND gate as its output is also active high. But since it is an active low type of pin, we use the NAND gate. For the following example, A15-A12 must be 0011 in order to select the chip. This results in the assignment of address 3000H to 3FFFH to this memory chip.
74LS138 as a decoder circuit
- The three inputs A, B, and C generate eight active low outputs Y0 – Y7
- We connect each of the Y output to CS of a memory chip, allowing us control over eight memory blocks via a single 74LS138.
- In the 74LS138, the inputs to A, B, and C activates the output. Also, there are three additional inputs, G2A, G2B, and G1.
- G2A and G2B are the enable input pins and are active low. G1 is the enable input pin that is active high.
- If anyone of the inputs G1, G2A, or G2B is not connected to an address signal, they must be activated permanently either by VCC or ground, depending on the activation level.
Now you might be wondering what does Ax, Dx, or ADx mean.
- ADx- Multiplexed address and data lines.
- Ax – The address lines determine the location from which the data is to be accessed or be sent.
- Dx- The data lines are used to send/receive the data to/from the external memory.
Let’s take an example. Suppose we want to activate the chip connected to output Y7 of the decoder.
Based on the simple working of a decoder, we know that the values of A, B, and C pins (A12, A13, A14) need to be 1 each. So for ABC = “111” we select the Y7 output, and the chip connected to it is now accessible.
But what range of addressable memory does this occupy? That will depend on the values of the entire 16-bit address line taken as a whole. Note that A15 also has to be 0 at all times since it is connected to G2A, the enable input pin that’s active low. With these four values fixed (A15A14A13A12 = “0111”), we can now vary the remaining pins from 0 to 1 each to get the final address range accessible via output pin Y7.
From the above table, we can see that the address range of Y7 is from 7000H to 7FFFH.
Programmable logic as a decoder circuit
- There are different types of programmable logic devices like PAL, GAL, etc., these are electronic components used to build reconfigurable digital circuits.
- PAL or Programmable Array Logic is PLD which consists of re-programmable AND logic and a fixed OR logic connected together.
- The advantage of these chips is that they are much more versatile since they can be programmed for any combination of address ranges.
- One disadvantage of these chips is that one must have access to a PAL/GAL software and burner, whereas the 74LS138 needs neither of these.
In this post, we are going to use 74LS138 as the 3:8 decoder circuit to interface the external RAM and ROM.
Control Signals and ports used to interface 8051
Let’s take a look at all the pins of the 8051 and study the pins that are used in interfacing external chips, communicating with them, and generating chip select logic.
ALE: PIN 30
- Port 0 of 8051 can be used to access the address bus and the data bus.
- The ALE pin is used for de-multiplexing the address and the data by connecting to the G-pin of the 74LS373 latch.
- It is also Active High
- 74LS373 comprises eight D flip flops.
- Flip flop data changes asynchronously when the Latch Enable (LE) is in High state.
- Whenever a clock pulse is applied, the input is passed on to the output as it is if the ALE pin is high.
- When the ALE pin is low, then the output is latched in the IC.
We have covered demultiplexing of AD pins using the 74LS343 latch in-depth over here.
PSEN: PIN 29
- This is an output pin.
- PSEN stands for “program store enable.”
- Connect this PSEN pin to the OE pin of the ROM to enable access to data.
- It is an active low output signal.
- It is used to enable/read external program memory (ROM).
- When [PSEN] = 0, then external program memory becomes enabled, and microcontroller reads the content of external memory location.
- Therefore, it is connected to (OE) of external ROM. It is activated twice every external ROM memory cycle.
- When [PSEN] = 1, then the data cannot be read from any external program memory, then the microcontroller has to depend on the on-chip ROM to store the program code.
EA: PIN 31
- EA is the External Access pin of 8051 microcontrollers.
- The EA pin is connected to GND to indicate that the code is stored completely in the external program memory (64kB).
- To use both on-chip ROM (4kB) and external ROM (60kB) together, the EA pin is connected to the +5V VCC supply.
- The overline represents active-low operation, i.e. Turns ON when a low pulse/signal is provided.
RD is used as a read control signal pin.
WR is used as a write control signal pin.
Port 0 and Port 2
- These ports provide a 16-bit address to access External Memory.
- P0: Multiplexed lower order address/data bus: AD0-AD7.
- P2: Higher-order address bus: A8-A15.
- When ALE = 0, P0 facilitates data path
- When ALE = 1, P0 facilitates address path
- We can address 2^16 = 64Kb memory (i.e. 64Kb code memory and 64Kb data memory) by these 16 address lines from A0 to A15.
- To extract the address from the P0 pins, we connect P0 to a 74LS373 and use the ALE pin to latch the address.
You can learn more about the Ports of 8051 here.
External ROM – For program/data
ROM is a type of non-volatile memory. The data is not lost, even if the power supply to the IC is taken off. ROM can be classified into:
- Flash EPROM
- Mask ROM
External addressable ROM for the 8051 is of 128KB of address space which is be divided into two parts:
- Program Code Space
- Data Memory Space
Program Code Space
To access the program space, we require a program counter (PC), it locates and fetches instructions. We use the MOVC A, @A+DPTR instruction to get data, where C stands for code. It is 64K bytes in size.
How to access program space?
For storing the program code, we can either use on-chip ROM or off-chip ROM or a combination of both on-chip and off-chip ROM depending on the status of the EA pin.
- Internal Program Memory (4KB) i.e. from 0000H to 0FFFH + External Program Memory (60KB) i.e. from 1000H to FFFFH. We can select this mode by making EA = 1. (Refer to fig.1).
- Total External Program Memory (64KB), i.e., over the entire range of 0000H to FFFFH. We can select this mode by making EA = 0. (Refer to fig.2)
- When we connect PSEN to the ground, then the 8051 microcontroller fetches the opcode from the external ROM.
- But, when we connect PSEN to VCC, the status of the PSEN is ‘not activated’ since it is an active low pin. Hence, the program memory is saved in the internal ROM of 8051 itself.
Circuit diagram to interface external program ROM with 8051
- Step 1: Connect EA pin to ground
- Step 2: Connect the PSEN to the CE and OE.
- Step 3: Then, Port 2 (P2.0 – P2.7) to A8 – A12 pins of ext. ROM.
- Step 4: Connect ALE to G of 74LS373 latch to enable it.
- Step 5: Next, connect the OC of 74LS373 to GND.
- Step 6: Connect Port 0 (P0.0 – P0.7), which consists of both address and data multiplexed into Port 0 to 1D – 8D pins of 74LS373 latch to demultiplex it and 1Q – 8Q of the latch to A0 – A7 of ext. ROM.
- Step 7: Connect Port 0 (P0.0 – P0.7) to D0 – D7 of the ext. ROM.
- Step 8: VPP of ext. ROM to VCC.
Code to interface external program ROM with 8051
Let’s say we want to move data stored from locations 4000H onwards in the external ROM to the location 40H in the internal RAM.
ORG 0000H MOV DPTR, #4000H ; Load DPTR with the location where data is stored MOV R0, #40H ; Load R0 with the int RAM loc where you want to save the data rep: MOV A, #00H ; Clear accumulator MOVC A, @A+DPTR ; Syntax to mode data from ext. ROM to accumulator MOV @R0, A ; Copy the value of accumulator in location pointed by R0 INC R0 ; Inc R0 to point to next int RAM location INC DPTR ; Inc DPTR to point to next ext. ROM location CJNE A, #00H, rep ; Repeat this process until 0 is received from the DPTR stay:SJMP stay ; Stay here END ; Let’s say that the data present at 4000H is ORG 4000H DB 1H, 2H, 0AH, 0F2H, 30H, 5CH, 2AH, 01H, 00H, FFH, 0 ; Here 0 is the stop bit that we’re assuming
Data Memory Space
To access the data memory space, we use the instruction MOVX A, @DPTR. Connect the RD pin (PIN 3.7) to the OE of data ROM and give an active low signal to the Chip enable (CE) pin of data ROM. Here we access the data from the external ROM containing the data and transferred to internal RAM.
Circuit diagram to interface external data ROM with 8051
Code to interface external data ROM with 8051
This is an assembly language program to read 100 bytes of data from external data ROM located at 1000H and send it to Port 1 of 8051.
ORG 0000H MYXDATA EQU 1000H ; 1000H, location where data is stored externally COUNT EQU 100 ; To receive all 100 bytes of data MOV DPTR, #MYXDATA ; Move DPTR to 1000H location MOV R0, #COUNT ; Load R0 with 100 rep: MOVX A, @DPTR ; Copy data from location pointed by DPTR to acc MOV P1, A ; Move contents of acc to P1 INC DPTR ; Inc DPTR to next ROM location DJNZ R0, rep ; Repeat until all 100 bytes are received stay: SJMP stay ; Stay here forever END
External RAM – For data
The RAM memory is called volatile memory since cutting off the power to the IC will result in the loss of data. An improvement of the default RAM is RAWM (read and write memory), which in contrast to ROM, to which we cannot write any data.
There are three types of RAM:
- Static RAM (SRAM)
- NV-RAM (non-volatile RAM)
- Dynamic RAM (DRAM)
We’re going to interface an SRAM chip.
How to access data space?
If we want to connect external data memory, i.e. SRAM, we must connect the RD (Pin 3.7) and WR (Pin 3.6) to the SRAM data memory. In writing data to external data RAM, we use the instruction.
MOVX @DPTR, A
We can also use NV-RAM, as it is the most efficient type of RAM whose memory remains even after the power to the IC is cut off. First off what is NV-RAM? It stands for non-volatile RAM and is the memory element which combines the best features of both RAM and ROM.
Features of NV-RAM:
- The read and write ability of RAM, plus the nonvolatility of ROM
- Extremely power-efficient SRAM cells built out of CMOS
- Consists of an internal lithium battery as a backup energy source
- Consists of intelligent control circuitry.
Circuit diagram to interface external RAM with 8051
- Step 1: Connect RD to OE of ext. RAM.
- Step 2: Connect WR to WE of ext. RAM.
- Step 3: Connect active low input of NAND gate to CE of external RAM, where the input to NAND gate are address lines A15, A14, and A13. We’ve given 0 1 0 to these lines to access the 8000H location of the external RAM.
Code to interface external RAM with 8051
This is an assembly language program to send 150 bytes of data or status of Port 2 to external RAM located at 6000H.
First of all, to access 6000H of the data memory, we have to send 0 1 1 to A15 A14 A13 respectively.
ORG 0000H RAMLOC EQU 6000H ; External RAM location = 6000H COUNT EQU 150 ; Variable count = 150d MOV DPTR, #RAMLOC ; Mov DPTR to point to ext. RAM location MOV R3, #COUNT ; Number of bytes of data rep: MOV A, P1 ; Copy status of P2 into acc MOVX @DPTR, A ; Copy the content of acc to the ext. RAM ACALL DELAY ; call a delay before repeating the process INC DPTR ; Inc DPTR to point to next location DJNZ R3, rep ; Repeat this until all the bytes of data are sent stay: SJMP stay ; Stay here forever END
Interfacing external program ROM, data ROM and external RAM with the 8051
Next, let’s interface both program ROM and data RAM to 8051, Let’s say we want to interface 16KB data RAM, 16KB program ROM, and 16KB of data RAM, then we’ll have to follow the following steps:
- Step 1: Calculate the number of address lines required to access 16KB of data, that is 214 = 16KB. Here, we require 14 address lines A0 – A13.
- Step 2: Decide the location of RAM and ROM, here we are going to interface program ROM from 0000H and data RAM from 8000H.
- Step 3: Select the decoder circuit, here we’re going to select 74LS138 decoder.
- Step 4: We do not need a decoder circuit for program ROM, but we have to connect the 74LS138 decoder to data ROM and data RAM.
- Step 5: Connect G1 to VCC, G2A, and G2B to ground.
- Step 6: Connect input A and B to P2.6 and P2.7 respectively, and the input C to ground.
- Step 7: We connect external program and data ROM, for that we can use an AND gate with its input being signal from RD (to access external data space) and PSEN (to access external program space) and output to OE of external ROM.
- Step 8: To interface the external RAM, we connect both RD and WR to WE and OE respectively of external RAM.
To sum up, in this post we understood how to interface an external memory element with the 8051 microcontroller family with the help of Port 0 and Port 2. We’ve learned and used several pins of the 8051 like ALE, PSEN, WR, RD, EA, and also looked at decoder circuits, all in all, to send or receive data to/from the external Program Memory and Data Memory.