What are buses? Why do we need buses in microprocessors?
In the world of computers and microprocessors, a bus is a connection between various components. These connections are meant for transfer of data among the components such as from CPU to memory or from CPU to a peripheral output device.
Buses can be of two types:
- Serial bus: A serial bus is a single line connection. As the name suggests, a group of bits is transferred one by one (i. e. serially) on that single line.
- Parallel Bus: A parallel bus is a group of a certain number of parallel lines connecting different components. In this type of bus, a group of bits is transferred at once, each bit on a separate line in a parallel manner.
The illustration below will help you visualize the concept of parallel and serial buses.
The microprocessor 8085 has its own bus structure responsible for the transfer of data between various components. Let us learn about it in detail.
Bus structure of 8085
Buses in 8085 are parallel in nature. The bus system of 8085 consists of 3 types of buses
- Address bus
The address bus is used to specify the address of a location in the memory or the address of an I/O device from which data transfer is to be made. It connects the CPU to the memory, input devices, and output devices. Note that in the above illustration, the address bus terminates at each of the above-mentioned components, pointing towards them. This tells us that the address bus is unidirectional. The address is specified by CPU and can only be directed from the CPU towards other devices and not the reverse.
- Data bus
The data bus, as the name suggests, is meant for the transfer of data. 8085 is an 8-bit microprocessor. So, the data bus is 8 bits wide. We will learn in detail what that means.
- Control bus
This is a parallel bus responsible for the signals that control the timing and other operations associated with data transfer between CPU and the memory or the I/O devices. This may seem a little daunting at present, but everything will be clear by the end of this post.
Address Bus in 8085
- As mentioned above, the address bus carries the address of a location in memory or address of an I/O device from where data is to be read or written.
- 8085 has a 16-bit address bus. That means it has 16 parallel lines to carry the 16 bits of an address. And each bit can be either 0 or 1.
- Hence, addresses can range from 0000H to FFFFH (65536 different addresses). In binary, it will be from 0000 0000 0000 0000 to 1111 1111 1111 1111. Each unique address refers to a byte (8 bits) of memory since 8085 is an 8-bit microprocessor.
It means that 8085 processes 8 bits of data at a time. It reads, writes, and performs arithmetic and logic operations on 8 bits at a time. There are certain microprocessors that process 16 bits (Intel 8086), 32 bits, and even 64 bits at one go.
So, we can say that microprocessor 8085 has a 16-bit address bus, and hence, it can support 216 bytes of memory (which is equivalent to 64 KiloBytes).
Data Bus in 8085
- 8085 Microprocessor processes 8 bits at a time. Hence, the data bus is of 8 bits i. e. 8 parallel lines to carry each bit of the 8 bits of data.
- In the above illustration of the bus structure of 8085, you can observe that the data bus has arrow ends on both sides, from CPU to the memory and from memory to the CPU. This tells us that the data bus is bidirectional.
- This is because data needs to flow in both directions. While reading, it flows from memory to CPU, and while writing, it goes from CPU to memory.
- For output devices, only write operation is performed, and for input devices, only read operation is performed. So, the data bus points in one direction only for the i/o devices.
- For the 16-bit address bus, 16 pins are needed. For the 8-bit data bus, another eight pins are needed. That is a lot of pins.
- To keep the total number of pins low, pins AD0-AD7 serves a dual purpose.
- There are eight A7-A15 pins for the higher 8 bits of the address. But for lower 8 bits of address as well as for moving data, the microprocessor uses the pins AD0-AD7.
- This is done by multiplexing the data and lower 8 bits of the address on AD0-AD7. It means that for some time interval, AD0-AD7 is used as an address bus, and during other time intervals, it is used as a data bus.
To use the lower 8 bits of the address to access the memory or to extract data, we need to demultiplex AD0-AD7. We need an external circuit that does that. The idea seems a little puzzling at first, but it is possible. Let us learn about it.
Demultiplexing of AD0-AD7 using IC 74LS373
The dual-purpose of the AD0-AD7 pins is achieved through multiplexing. In simple words, multiplexing allows us to use the pins of a microprocessor for more than one function.
Pros of multiplexing of pins in a microprocessor: Since each pin can serve multiple purposes, the total number of pins can be reduced.
Cons of multiplexing of pins in a microprocessor: We need additional circuitry to demultiplex these pins to allow them to serve their multiple purposes individually.
But for extracting the data and the lower 8 bits of the address, we demultiplex AD0-AD7 using IC 74LS373. Let me explain it through an example.
First, let us get to know the working of IC 74LS373.
- IC 74LS373 is an IC with 20 pins.
- It consists of 8 latches. (A latch is a digital component that can hold on to a bit of data. At the risk of oversimplification, it is a memory unit to hold one bit of data. You can read more about latches and flip-flops here.)
- Each latch is controlled by two signals: Latch Enable (LE) and Output Enable (OE).
- So, there are eight pairs of inputs and outputs, one for each latch. And the two pins to give LE and OE signal.
- This accounts for 18 pins.
- The remaining two pins VCC and GND are used to power up the IC.
- Inputs are provided at the eight input pins D0-D7.
- If the LE is high, inputs at D0-D7 are reflected exactly at the corresponding outputs O0-O7.
- When the LE signal goes low, values of inputs at that instant are latched (or trapped) inside and are available at the output.
- All this time, we assume Output Enable signal to be active.
Now, since we are familiar with the working of IC 74LS373, let us look at how the dual role of AD0-AD7 is achieved. It would be easy to understand it through an example with a timing diagram and the circuit connection shown in the illustrations below.
Let us go through the process step by step. Let us assume that instruction
MOV C, A is to be executed. For executing the instruction, the microprocessor first has to read the opcode (hex code for the instruction) stored at 2005H. The hex code here is 4FH. You can ignore things and just look at it as “microprocessor reading data at a memory location having the address 2005H.”
The whole process consists of 4 T states or 4 clock cycles (refer to the timing diagram above). In the first clock cycle, the higher 8 bits of the address (20H) are loaded in A8-A15. At the same time, the lower 8 bits of the address (05H) are issued at pins AD0-AD7. Also, the ALE signal issued by the microprocessor is high, telling that AD0-AD7 contains the lower 8 bits of the address. (i.e., the pins are currently functioning as address pins.)
Notice that in the circuit diagram, the ALE signal is connected to the LE (latch enable) pin of the IC. This ensures that the address received at the input of the 74LS373 IC (05H) is reflected at its output (i.e., the output of the 74LS373 IC is 05H).
Near the end of the first clock cycle, the ALE signal goes low. Whatever bits were there on AD0-AD7 (in this case, 05H) at that instant are latched (frozen) in the IC. That means, those bits are present at the output of the IC and are not affected by the values on AD0-AD7 anymore.
You see, the entire reason behind this exercise is to help the pins (AD0-AD7) carry two different types of values on the same path. We do this by carrying one of the values first (the address), handing it over to the IC with the latches (memory units) to hold on to, and then getting the other set of values.
Now, all the 16 bits of the address are available. Higher 16 bits at A8-A15 and lower 8 bits at the outputs of the IC. This means that AD0-AD7 is free now. It can now be used as the data bus. Now, during the second and third clock cycles, 8-bit data to be fetched (4FH) is loaded on AD0-AD7 from memory and is retrieved by the microprocessor. Note that in this step, AD0-AD7 is being used as the data bus.
This is how the demultiplexing of AD0-AD7 works.
Control Bus in 8085
This is a group of parallel lines used by the microprocessor to issue control signals such as IO/M, RD, WR. As you have seen in our post on the pin diagram of 8085, there are three different pins at which the microprocessor issues these control signals.
- Pin 30 for IO/M
- Pin 31 for WR
- Pin 32 for RD
Control signals are the signals used to control the operations related to memory and other associated peripherals.
The same data bus is used for read as well as write operations. These two types of operations also need to be done at two possible locations (memory or I/O). How do we control which operation (read/write) is supposed to be done at which location (Memory/IO)?
The control signals issued by the microprocessor distinguish between these different types of operations. The three control signals are explained here in brief, followed by a table explaining these control signals and status signals during various processes.
- IO/M (Control signal)
This signal specifies whether the operation (read or write) is being performed on memory or an i/o device.
- RD (Control signal)
Goes low for read operation and becomes high otherwise.
- WR (Control signal)
Goes low for a write operation and becomes high otherwise.
|Machine cycle||IO/M||S1 S0||Control signals|
|Opcode Fetch||0||1 1||RD= 0|
|Memory Read||0||1 0||RD= 0|
|Memory Write||0||0 1||WR = 0|
|I/O Read||1||1 0||RD= 0|
|I/O Write||1||0 1||WR = 0|
|Interrupt Acknowledge||1||1 1||INTA = 0|
A bar or overline above signals RD and WR indicates that these are active low signals. It means that their functionality is implemented when their value is low or ‘0’. For example, an operation will be a read operation when RD= 0.
Generation of control signals using 74138 decoder
So far, we have seen that 8085 issues three control signals; IO/M to specify if the operation is for an I/O device or a memory and RD and WR to specify if the operation is a read operation or a write operation. Since these signals deal with the two categories (read/write and memory/io) separately, it makes it a little complex to interface the microprocessor with the memory or i/o device.
You can understand it like this.
Suppose we interface a memory with the microprocessor. While performing operations, we need to tell the memory if we are talking to it or not. For that, we need IO/M signal. We also need to tell the memory if we want to read data from it or write the data. For this purpose, we need RD and WR signals. Similar is the case with an i/o device. For interfacing, we will need all the three signals and things will become a little complex.
To simplify things, we try to generate four direct and easy to understand signals from the above three signals.
- MEMR (Memory Read)
- MEMW (Memory Read)
- IOR (I/O Read)
- IOW (I/O Read)
There is more than one way of achieving this. But we are going to do it using the 74138 decoder. You can read more about the 3:8 decoder here.
Before we proceed with the details, let us get to know the 74138 Decoder.
74LS138 Decoder IC
- The decoder IC 74LS138 has 16 pins in total.
- Three input pins A, B, C (I0, I1, and I2) and eight output pins Y0-Y7.
- There are three enable input pins. Two of them are active low. These three pins are used to enable input pins of the IC. (These are for additional functionality, and we should not worry about that here. We just connect the two active-low pins to ground, and the remaining enable input pin to Vcc.)
- The remaining two pins Vcc and GND are meant to power up the IC.
The truth table of the IC is given below.
Interfacing the 74LS138 decoder with 8085
The following circuit diagram shows the connections.
As explained above, we connected the two active low input enable pins to ground, and the other input enable pin to +5V. Control signals are connected at the inputs, as shown. So, the new output table (you may call it truth table) will be
|Type of operation||Inputs||Outputs||Output result|
As it is evident from the output table, during a memory read operation, C=IO/M = 0 , B=RD = 0 , A=WR = 1 . This combination of input corresponds to the second row of the truth table of the IC we saw above in which Y1 = 0 and the rest of the output pins are high. So, we can say that the output pin (At this set of values of the output, 11111101) gives us the control signal for memory read operations. So, output Y1 represents the signal MEMR.
Signals with bar or overline above them are active low. That means these signals are active when their value is 0 or low.
Now, we can directly connect the four signals MEMR, MEMW, IOR, IOW to the memory or the device we want to interface.
MEMR signal will be active only when there is a read operation and that read operation is on the memory. Unlike RD signal, it will not be activated if there is a read operation on an i/o device. This is how this generation of control signals makes things simpler.
I hope the Bus organization and Generation of control signals are clear by now. If you still have some doubts or want to learn something more, leave a comment below and we will get back to you.