View Course Path 8085 Microprocessor MCQ | Quiz | Interview Questions Published March 7, 2020 | Updated April 23, 2020 1. A nibble corresponds to2 bits4 bits8 bits16 bits 2. The 8085 has five sign flagsTrueFalse 3. The Z flag is set when an ALU operation results in a 0 outputTrueFalse 4. Assertion (A): Microprocessor 8085 has an on-chip oscillator with an inbuilt crystal. Reason (R): For frequency stability crystal oscillator is preferred.Both A and R are correct and R is the correct explanation of ABoth A and R are correct but R is not the correct explanation of AA is correct R is wrongA is wrong R is correct 5. If the source and destination addresses are made implicit the length of instruction is reduced.TrueFalse 6. Which of the following has volatile memory?Magnetic TapeRAMHard DiskDiskette 7. If a microprocessor uses a 5 MHz oscillator. The duration of one T state is1 μs0.333 μs 0.2 μs 2 μs 8. What type of instructions can potentially change the sequence of operations in a program?Logical instructionsData transfer instructionsBranch instructionsArithmetic instructions 9. Seven address and data buses are multiplexed in 8085TrueFalse 10. The Sign flag is set when the contents of the accumulator become negative after an ALU operation.TrueFalse 11. Consider the following mnemonics MOV ADD LXI ADI1 and 2 only2 and 3 only1, 2 and 3 only1, 2, 3 and 4 12. Handshaking programmed data transfer is also known asAsynchronous transferSynchronous transferInterrupt driver transferBoth (a) and (c) 13. The addressing mode shown in the given figure is Immediate addressing modeDirect addressing modeRegister indirect addressing modeRegister addressing mode 14. Which of the following 8085 instructions affect all flags except the CY flag?ADC rINR rSEE MACI data 15. The issue of a timing difference between a fast processor and slow memory is resolved byusing a processor that's capable of waitingusing an external bufferusing a coprocessornone of these 16. In 8085, the RST instruction will cause an interrupt _______.only if interrupts have been enabled by the EI (Enable interrupt) instructiononly if the interrupt mask bit is set to 0only if an ISR is not actively executingevery time it's executed 17. Which of the following are buses present in 8085?Address BusDMA busMemory BusControl Bus 18. The values of odd and even parity flags are ___ and ___ respectively0, 11, 00, 01, 1 19. Which mode of Data Transfer Schemes (DTS) has the highest efficiency?Cycle stealing modeBurst modeNoneBoth 20. The content of the HL pair after the execution of the following instructions is ___. XRA A MOV L, A MOV H, L INX H DAD H0000H0001H0011H0002H 21. A stack pointer stores the ____.Address of bottom of stackAddress of instruction being executedAddress of instruction to be executedAddress of top of stack 22. The register which holds the information about the nature of results of arithmetic and logic operations is called asCondition code registerAccumulatorFlag registerProcess status register 23. An 8-bit microprocessor signifies that the processor has an8-bit data bus8-interrupt lines8-bit controller8-bit address bus 24. What is the purpose of the READY signal in 8085It's used to provide WAIT states when the 8085 is communicating with a slow peripheral deviceIt indicates that the 8085 is ready to receive inputsIt indicates that the 8085 is ready to provide Direct Memory AccessIt indicates that the 8085 is ready to send outputs 25. For memory mapped I/O, which of the following is true?Devices are accessed using IN and OUT instructionsDevices have 8-bit address lineThere can be maximum of 256 input devices and 256 output devicesArithmetic and logic operations can be directly performed with the I/O data 26. RST0 - RST7 are the __________ in 8085.hardware interrupts logical interrupts software interrupts conditional interrupts 27. The Program Counter (PC) in a microprocessor is used tospecify the address of the instruction to be executedspecify the address of the instruction currently executingspecify the number of instructions executednone of these 28. Upon the execution of the RET instruction:PC gets incrementedcontrol goes directly to the next instruction after the calling instruction without any operationcontrol goes directly to the next instruction after the calling instruction without any operation and also PC will get incrementedtop of the stack will get popped and get assigned to the PC 29. POP B is a1 byte instruction2 byte instruction3 byte instruction4 byte instruction 30. If you wish to save the value of the accumulator on the stack, which of the following instruction will you use?PUSH PSWPUSH APOP PSWPUSH SP 31. All jump/branch instructions in 8085 use ___________ addressingAbsoluteImmediateIndirectImplicit 32. Stack pointer is stored inRAMROMeither RAM/ROMMicroprocessor 33. Which of the following is not true during the execution of an interrupt service routine, which does not contain any EI instructionsthe microprocessor can be interrupted by a non-mask able interrupt the microprocessor cannot be interrupted by any interruptthe microprocessor cannot be interrupted by any maskable interrupt all interrupts except non-maskable interrupt are disabled 34. After the execution of CMP A instructionZF is set and CY is unchangedZF is reset and CY is setZF is set and CY is resetZF is reset and CY is unchanged 35. The 8085 microprocessor enters into bus idle machine cycle wheneverRST 7.5 is recognizedINTR interrupt is recognizedDAD RP instruction is executednone of the above 36. The content of the A15-A8 (higher-order address lines) while executing “IN 8-bit port address” instruction areirrelevantall bits reset (i.e. 00H)all bits set (i.e. FFH)same as the content of A7-A0 37. Select the correct statement(s). In 8085, the data bus and the address bus are multiplexed in order to:Increase the speed of the microprocessorReduce the number of pinsConnect more peripheral chipsReduce power consumption 38. Both, the ALU and the control section of 8085 employs which special-purpose storage location?RegistersDecodersBuffersAccumulator 39. What will be the value in the memory location 7101H after the execution of the following code? The data at memory location 7100 is A7H. LXI H,7100H MOV A, M CMA INR A STA 7101H HLT 59H58H5AHnone of these 40. A programmer's model is ____.list of all I/O devices that can be connecteddiagrams of the internal bus architecturepart of the block diagram that a programmer can affect using the instruction setthe entire block diagram Loading... Security Question: What is the name of this website?