Verilog code for D flip-flop – All modeling styles

Updated for 2025:

In this article, we will explore the design and implementation of the D flip-flop using Verilog through three key abstraction levels: Gate-Level, Dataflow, and Behavioral modeling. We will also focus on using the latest tools and techniques to simulate, test, and optimize the design of flip-flops for modern digital systems. As digital designs have evolved, new trends such as hardware description languages (HDLs) integration with FPGA and ASIC development have become increasingly significant, especially in fields like IoT, AI, and high-speed computing. We’ll also walk through the RTL schematic generation for a D flip-flop and guide you through writing testbenches in Verilog using cutting-edge simulation tools for accurate and efficient verification.

By the end of this tutorial, you will have hands-on experience in modeling a D flip-flop using Verilog’s highest abstraction levels and a solid understanding of how to simulate and deploy the design on modern hardware platforms.

What is D flip flop?

A D flip-flop (also known as data flip-flop) is a type of sequential digital circuit used in electronics and digital systems for storing a single bit of data. It is one of the most basic building blocks in memory systems, shift registers, and counters. D flip-flops are fundamental in many applications such as register files, timing circuit, and finite state machines (FSMs).

A D flip-flop stands for data flip-flop. But sometimes it can also be interpreted as delay flip-flop. The reasoning behind this interpretation comes from the fact that the D flip-flop delays the input data until the next clock edge, storing the value until it is transferred to the output.

Inputs:

• D input: The data or value that will be stored in the flip-flop.
• CLK input: A signal that triggers the storage of the data. The flip-flop captures the value of the D input on the rising or falling edge of the clock signal (depending on the design).

Outputs:

• Q: This is the output that reflects the value of the D input after the clock edge.
• Not-Q (Q’): This is the complimentary output, always the opposite of Q.

As we proceed, we will see how we can design a D flip flop using different levels of abstraction

Gate level modeling

Gate level modeling uses primitive gates available in Verilog to build circuits. Hence, we need to know the logic diagram of the circuit we want to design.

From the above circuit, we can see that we need four NAND gates and one NOT gate to construct a D-flip flop in gate-level modeling.

Gate level Modeling of D flip flop

As always, the module is declared listing the terminal ports in the logic circuit.

module d_ff_gate(q,qbar,d,clk);

Note that we declare outputs first followed by inputs since built-in gates also follow the same pattern. Now, let’s declare the input and output ports.

input d,clk;
output q, qbar;

wire dbar;       //output of not1
wire nand1_out;  // output of nand1
wire nand2_out;  // output of nand2

not ( dbar,d);
nand (nand1_out,clk,d);
nand (nand2_out,clk,dbar);
nand (q,qbar,nand2_out);
nand (qbar,q,nand1_out);

module d_ff_gate(q,qbar,d,clk);
input d,clk;
output q, qbar;
wire dbar; //output of not1
wire nand1_out; // output of nand1
wire nand2_out; // output of nand2
not ( dbar,d); 
nand (nand1_out,clk,d);
nand (nand2_out,clk,dbar);
nand (q,qbar,nand2_out);
nand (qbar,q,nand1_out);
endmodule

module dff_dataflow(d,clk,q,qbar);
input d,clk;
output q, qbar;

assign q = clk?d:q;
assign qbar = clk?!d:qbar;

module dff_dataflow(d,clk,q,qbar); 
input d,clk; 
output q, qbar;

assign q = clk?d:q;
assign qbar = clk?!d:qbar;

endmodule

module dff_behave(d, clk, q, qbar);
input d,clk;
output reg q, qbar;

always@(posedge clk)
begin
.....
end

always@(posedge clk)
begin
q <= d;
qbar <= !d;
end

module dff_behavioral(d,clk,q,qbar);
input d, clk;
output reg q, qbar;

always@(posedge clk)
begin
q <= d;
qbar = !d;
end
endmodule

module dff_behavioral(d,clk,clear,q,qbar); 
input d, clk, clear; 
output reg q, qbar; 
always@(posedge clk) 
begin
if(clear== 1)
q <= 0;
qbar <= 1;
else 
q <= d; 
qbar = !d; 
end 
endmodule

module dff_behavioral(d,clk,clear,q,qbar); 
input d, clk, clear; 
output reg q, qbar; 
always@(posedge clk or posedge clear) 
begin
if(clear== 1)
q <= 0;
qbar <= 1;
else 
q <= d; 
qbar = !d; 
end 
endmodule

Like in Gate level modeling, we analyze the logic design for structural modeling. We will consider the gates required to build the design. But, instead of using in-built gates, we take each gate and create separate modules that will be integrated to form the whole circuitry.

In the case of D-flip flop, we have a NOT and four NAND gates that build the circuit.

Hence, we have to structurize each gate with their respective module.

Structural Modeling of D flip flop 

To start with code, we will first structurize the NAND gate.

We declare the module as nand_gate. The input and output ports are then declared.

module nand_gate(c,a,b);
input a,b;
output c;

Then, we use assign statement to write the logical expression for NAND.

assign c= ~(a & b);

The endmodule keyword is used for representing the end of the module.

Similarly, we do for NOT gate

module not_gate(f,e);
input e;
output f;

assign f = ~e;
endmodule

Now, we have to integrate these lower modules to form our D-flip flop. In order to do that, we use module instantiation. First, start with the name of the lower hierarchy module (defined and declared above) and write the name of the instance of your choice. The port-list will contain the output signals, followed by the input ones.

For example,

nand_gate nand1(x,clk,d);

Here,

1. module-name :- nand_gate
2. instance name:- nand1
3. output port:- x(intermediate signal)
4. input ports:- d and clk

Do the same for the rest of the instances

 
not_gate not1(dbar,d); 
nand_gate nand1(x,clk,d); 
nand_gate nand2(y,clk,dbar); 
nand_gate nand3(q,qbar,y); 
nand_gate nand4(qbar,q,x); 
endmodule

Hence, the final structure code will be:

module nand_gate(c,a,b); 
input a,b; 
output c; 
assign c = ~(a&b); 
endmodule

module not_gate(f,e); 
input e; 
output f; 
assign f= ~e; 
endmodule

module d_ff_struct(q,qbar,d,clk);
input d,clk; 
output q, qbar; 
not_gate not1(dbar,d); 
nand_gate nand1(x,clk,d); 
nand_gate nand2(y,clk,dbar); 
nand_gate nand3(q,qbar,y); 
nand_gate nand4(qbar,q,x); 
endmodule

Testbench

A testbench is an HDL module that is used to test another module, called the device under test (DUT). The test bench contains statements to apply inputs to the DUT and, ideally, to check that the correct outputs are produced. The input and desired output patterns are called test vectors.

Let’s see how we can write a test bench for D-flip flop by following step by step instruction

//test bench for d flip flop
//1. Declare module and ports

module dff_test;
reg D, CLK,reset;
wire Q, QBAR;

//2. Instantiate the module we want to test. We have instantiated the dff_behavior

dff_behavior dut(.q(Q), .qbar(QBAR), .clear(reset), .d(D), .clk(CLK)); // instantiation by port name.

//3. Monitor TB ports
$monitor("simtime = %g, CLK = %b, D = %b,reset = %b, Q = %b, QBAR = %b", $time, CLK, D, reset, Q, QBAR);

//4. apply test vectors
initial begin
  clk=0;
     forever #10 clk = ~clk;  
end 
initial begin 
 reset=1; D <= 0;
 #100; reset=0; D <= 1;
 #100; D <= 0;
 #100; D <= 1;
end 
endmodule

RTL Schematic

Here’s how the RTL Schematic will look if we peek into the elaborate design of the behavioral model of the D-flip flop without clear input.

With synchronous clear input,

And with asynchronous clear input,

Simulated Waveforms

D flip flop Without Reset

In this waveform, we can see that the Q and Q’ will be reset state at the positive cycle after clear is activated

In this waveform, we can see that the Q and Q’ will be in the reset state as soon as clear is activated.

Conclusion

In this article, we’ve explored the design and implementation of a D flip-flop using multiple modeling styles in Verilog, including Gate-level, Dataflow, and Behavioral modeling. Each approach offers unique benefits, from the simplicity and directness of gate-level modeling to the higher-level abstraction and ease of use in behavioral modeling. We also examined how to incorporate features like synchronous and asynchronous clear inputs, which are essential for resetting the flip-flop’s state in various applications.

D flip-flops are fundamental building blocks in digital design, playing a crucial role in memory storage and synchronization within sequential circuits. Understanding how to implement and test these flip-flops effectively across different modeling styles equips designers with the tools needed to create more complex systems such as registers, counters, and shift registers.

By grasping these core concepts, you will be better prepared to design and simulate robust digital systems that meet modern requirements, especially in areas like high-speed computing, signal processing, and embedded systems. Whether you’re a beginner or looking to refine your Verilog skills, mastering the D flip-flop’s design and testing techniques is a significant step forward in your digital design journey.

Frequently Asked Questions about D flip-flop

What is the difference between a D flip-flop and a D latch?

A D flip-flop and a D latch both store a single bit of data, but the key difference lies in the clocking mechanism. A D latch is level-sensitive, meaning it updates its output whenever the clock signal is high. In contrast, a D flip-flop is edge-triggered, meaning it only updates the output on the rising or falling edge of the clock signal.

What is the purpose of Q’ (Q bar) in a D flip-flop?

The Q’ (Q bar) output is the complement or inverse of the Q output. If Q is 1, Q’ will be 0, and vice versa. This dual output allows for applications where both the normal and inverted states of the flip-flop are needed in digital circuits.

What is the difference between synchronous and asynchronous clear in a D flip-flop?

In a synchronous clear, the flip-flop’s output is reset when the clear signal is activated during the clock edge. The reset operation is synchronized with the clock. In an asynchronous clear, the reset occurs immediately when the clear signal is triggered, independent of the clock signal.

Why is the reg data type used in behavioral modeling of D flip-flops?

The reg data type in Verilog is used in behavioral modeling because it allows the flip-flop to retain its value until a new assignment is made. It is required when writing sequential logic (such as in flip-flops) because reg can hold its value between clock cycles, unlike other data types that are used for combinational logic.

Can the D flip-flop be used for memory storage in larger digital systems?

Yes, D flip-flops are often used as memory elements in larger digital systems like registers, shift registers, and memory arrays. Multiple D flip-flops can be combined to store multi-bit data, and their predictable behavior makes them ideal for applications in data storage and synchronization.

What are the advantages of using Verilog for designing flip-flops?

Verilog is a hardware description language (HDL) that allows for efficient simulation, synthesis, and testing of digital systems. It is widely used because it supports multiple levels of abstraction (gate, dataflow, and behavioral modeling), making it suitable for a range of designs, from simple to complex. Additionally, Verilog’s modular nature helps in reusability and scalability of digital designs.

How do I simulate a D flip-flop in Verilog?

To simulate a D flip-flop in Verilog, you must write a testbench that applies various input patterns to the flip-flop and monitors the output. The testbench will apply clock pulses, set/reset signals, and the data input while observing how the Q and Q’ outputs behave in response to these inputs.

What are some common applications of D flip-flops in digital circuits?

D flip-flops are commonly used in applications such as:

• Registers: To store multi-bit data in processors.
• Counters: To count events or clock cycles in sequential circuits.
• Shift Registers: For shifting data in communication systems or memory devices.
• Timing and synchronization: To synchronize signals in systems with multiple clock domains.