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Verilog Quiz | MCQs | Interview Questions

1. The default value for reg data type is ______.

2. The possible value(s) of the == operator are:

3. To suspend a simulation, you can use this system task command.

4. ______ operator usually comes before the operand.

5. @posedge means

6. We can overwrite the value of a parameter during module instantiation using ______.

7. The wait statement is

8. In continuous assignment statement LHS can be

9. To trigger an event, we can use the following operator.

10. ______ defines special parameters in the specify block.

11. To introduce delays in a circuit, we can use a _________.

12. In most synthesis tools, what will happen when a signal that is needed in a sensitivity list is not included?

13. The keyword deassign is a

14. In non-blocking assignment, the compiler

15. The phenomenon of clock skew is found in ________.

16. Cycle based simulation is useful for


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