Verilog Code for AND Gate – All modeling styles

Updated for 2025: Verilog remains one of the most widely used Hardware Description Languages (HDL) for designing and simulating digital circuits. In 2025, Verilog-based FPGA development continues to be essential for AI accelerators, embedded systems, and ASIC prototyping.

This article has been reviewed and updated to ensure accuracy and relevance. We’ve also:

• Improved readability and explanations.
• Enhanced testbench examples for better simulation results.
• Added best practices to optimize your Verilog code.

Introduction to Verilog Code for AND Gate

In this article, we’ll explore how to implement an AND gate in Verilog using three different modeling styles: Gate Level, Dataflow, and Behavioral modeling. Each modeling approach offers a unique way to define the logic, helping developers choose the best fit based on design complexity.

By the end of this guide, you’ll have a fully functional Verilog code for AND gate, including a testbench to verify its correctness.

Gate Level Modeling of AND Gate in Verilog

Gate-level modeling in Verilog involves using predefined logic gats to design circuits. Since AND gates are a fundamental part of digital logic, Verilog provides built-in AND primitives to describe their behavior.

We can design a logic circuit using basic logic gates with Gate level modeling.

Logic Circuit of the AND gate

The AND gate is a primary logic gate where the output is equal to the product of its inputs. The output of this gate is high only if both the inputs are high else the output is low. Here’s the logical representation of the AND gate.

Verilog code for AND gate using gate-level modeling

The code for the AND gate would be as follows.

module AND_2(output Y, input A, B);

We start by declaring the module. module, a basic building block in Verilog HDL is a keyword here to declare the module’s name. The module command tells the compiler that we are creating something which has some inputs and outputs. AND_2 is the identifier. Identifiers are how we name the module. The list in parenthesis is the port list containing input and output ports (You can read more about module declaration here). Then we write:

and(Y, A, B);
endmodule;

Here and is the operation performed on A, B, to get output Y. endmodule terminates the module. Verilog has this functionality to describe the circuit at the gate level. The compiler understands that the and operation means that it has to get a product of the inputs.

Here, you can look on the complete code:

module AND_2(output Y, input A, B);
    and(Y, A, B); 
endmodule

Dataflow Modeling of AND Gate in Verilog

Compared to gate-level modeling, dataflow modeling in Verilog is a higher level of abstraction. What this means is, you don’t really need to know the circuit design. That’s really helpful because gate-level modeling becomes very complicated for a complex circuit.

Hence dataflow modeling is a very important way of implementing the design. All you need to know is the boolean logic equation of the output of the circuit in terms of its inputs. We use continuous assignments in dataflow modeling in most of the designs. The continuous assignments are made using the keyword assign. You’ll see how it works in a bit.

Equation of the AND gate

As we can observe from the diagram above, the boolean equation would be Y = A & B.

Verilog code for AND gate using data-flow modeling

We would again start by declaring the module.

module AND_2_data_flow (output Y, input A, B);

Then we use assignment statements in data flow modeling. Using

assign Y = A & B; 
endmodule

Just like the and operation, the & logical operator performs a binary multiplication of the inputs we write. Then endmodule is used to terminate the module.

This is what the Verilog code looks like for AND Gate using Dataflow Modeling

module AND_2_data_flow(output Y, input A, B);
  assign Y = A & B; 
endmodule

To summarize:

• assign Y = A & B; → Implements the AND operation using the & operator.
• No need to manually define gates—Verilog automatically infers them from the Boolean equation.

Behavioral Modeling of AND Gate in Verilog

Behavioral modeling is the highest level of abstraction in the Verilog HDL. All that a designer need is the algorithm of the design, which is the basic information for any design. This level simulates the behavior of the circuits; the details are not specified. That’s helpful because the designer does not have to deal with complicated circuitry or equations. Just a simple truth table would suffice. Behavioral modeling describes circuit functionality using control statements like if-else, case, and always blocks

AND gate’s truth table

Equation from the truth table

Simply by minimization, (or you may arrive by k-maps), we can state that:

Y = A.B or say Y = A & B.

Verilog code for AND gate using behavioral modeling

Again, we begin by declaring module, setting up identifier as AND_2_behavioral, and the port list.

module AND_2_behavioral (output reg Y, input A, B);

In this case, the port list includes the output and input ports. When our level of abstraction is behavioral level, then we use reg datatype in the output ports. The reg data object holds its value from one procedural assignment statement to the next and means it holds its value over simulation data cycles.

Then we write,

always @ (A or B) begin
  .....
end

Using the always statement, a procedural statement in Verilog, we run the program sequentially. (A, B) is known as the sensitivity list or the trigger list. The sensitivity list includes all input signals used by the always block. It controls when the statements in the always block are to be evaluated. @ is a part of the syntax, used before the sensitivity list. In Verilog, begin embarks and  end concludes any block which contains more than one statement in it.

Note that the always statement always @(Y, A) could be written as always @ *. * would mean that the code itself has to decide on the input signals of the sensitivity list. Now, we have,

always @ (A or B) begin
   if (A == 1'b1 & B == 1'b1) begin
       Y = 1'b1;
   end
   else 
       Y = 1'b0; 
end

Here is the full code:

module AND_2_behavioral (output reg Y, input A, B);
always @ (A or B) begin
    if (A == 1'b1 & B == 1'b1) begin
        Y = 1'b1;
    end
    else 
        Y = 1'b0; 
end
endmodule

`include "AND_2_behavioral.v"
module AND_2_behavioral_tb;
reg A, B;
wire Y;
AND_2_behavioral Instance0 (Y, A, B);
initial begin
    A = 0; B = 0;
 #1 A = 0; B = 1;
 #1 A = 1; B = 0;
 #1 A = 1; B = 1;
end
initial begin
    $monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
    $dumpfile("dump.vcd");
    $dumpvars();
end
endmodule

When simulating the Verilog AND gate testbench, the waveform confirms that the output (Y) is HIGH (1) only when both inputs (A and B) are HIGH (1).