Avisekh Ghosh


8 Articles
0 Courses
Joined: May 2020

Courses

Articles

D algorithm - combinational atpg in dft vlsi

D algorithm – Combinational ATPG in DFT (VLSI)
ATPG in DFT

Automatic Test Pattern Generation (ATPG) in DFT (VLSI)
jtag boundary scan in dft VLSI

Introduction to JTAG Boundary Scan – Structured techniques in DFT (VLSI)
internal scan chain structured DFT method

Internal Scan Chain – Structured techniques in DFT (VLSI)
fault collapsing methods - reduction, equivalence, dominance

Fault Collapsing methods and Checkpoint Theorem in DFT (VLSI)
test generation methods - Truth table, analytical xor method, path sensitization methods in DFT

Test Generation Principles in DFT (VLSI)
Faut Modeling in chip design - VLSI (DFT)

Fault Modeling in Chip Design – VLSI (DFT)
what is DFT design for testability introduction

What is Design for Testability (DFT) in VLSI?

Interesting facts