View Course Path Digital Electronics Quiz | MCQs | Interview Questions Published March 18, 2020 | Updated April 23, 2020 Loading... 1. How many flip-flops are required to make a MOD-32 binary counter?35645 Loading... 2. A MOD-16 ripple counter is holding the count 1001_{2}. What will the count be after 31 clock pulses?1000100110101011 Loading... 3. The circuit shown below is a _______. Ring counterDecade counterPIPO shift registerPISO shift register Loading... 4. Two cascaded decade counters will divide the input frequency by ________.10100100020 Loading... 5. Any divide-by-N counter can be formed by using external gating to ________ at a predetermined number.ResetLOWPresetHIGH Loading... 6. The final count of a modulus-11 binary counter is ________.1000110010101011 Loading... 7. When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.ReciprocalLogProductExponent Loading... 8. A BCD counter is a ________.divide-by-10 counterDecade counterbinary counterfull-modulus counter Loading... 9. The flip-flops of a 4-bit ripple counter have a propagation delay from clock to Q output of 10 ns, each. For the counter to recycle from 1111 to 0000, it takes a total of ________.10ns30ns40ns45ns Loading... 10. Which of the following statements are true regarding a synchronous up/down counter?It can count in any direction but direction can't be changed once counting has startedThe direction can be changed midway, but the counter has to be reset before that can be doneThe counter can be reversed at any moment, no strings attachedThe direction cannot be changed midway, and when changed the counter has to be reset first Loading... 11. The delay problems encountered with asynchronous counters are removed with synchronous counters because the:input clock pulses are applied simultaneously to each stageinput clock pulses are not used to activate any of the counter stagesinput clock pulses are not used to activate any of the counter stagesinput clock pulses are applied only to the first and last stages Loading... 12. Which is not an example of a truncated modulus?981115 Loading... 13. _____ counter is a type of a shift register counter.BCDRingDecadeBinary Loading... 14. The resolution of an n bit DAC with a maximum input of 5 V is 5 mV. The value of n is …….10100111 Loading... 15. If A=B=D=0, and C=1, the value at OUT will be? LOWHIGHEither of the above, depending on the magnitudeZ Loading... 16. A ______ enables us to display a BCD code on a seven-segment display.EncoderDecoderMultiplexerDemultiplexer Loading... 17. If a BCD to seven-segment decoder sends 0111 to a seven-segment display, the segments that will go LOW are:a,b,cf,g,e,df,g,eall Loading... 18. _______ is the basic memory unit in digital electronics and hold 1-bit of data.EncoderNAND gateFlip-flopEXOR gate Loading... 19. We can use _______ and _______ to make a full addera half adder, an OR gatetwo half adders, an OR gatetwo half adders, two OR gatestwo half adders, two NOT gates Loading... 20. (7BF)_{16} = (?)_{2}1111 1011 10100111 1011 10100111 1011 10110111 1111 1010 Loading... 21. (?)_{8} = (E8)_{16}350250530333 Loading... 22. The decimal equivalent of the 2's complement of 11100101 is _________.0001101110011011+27-27 Loading... 23. Find Q AB + BC(B + C)AB + AC(B + C)BC + AB(B + C)AB + BC(A + B + C) Loading... 24. Select the Universal Logic gates from the following optionsNOTNANDNOREXNOR Loading... 25. Asynchronous circuits that change state immediately when enabled are called __________.Clock driven circuitsEvent driven circuitsPulse driven circuitsNone of these Loading... 26. We can erase the contents of an EPROM by exposing it to ________.MicrowavesUV raysInfrared raysGamma rays Loading... 27. This digital logic family has the lowest power dissipationTTLCMOSRTLDTL Loading... 28. Select the volatile memories from the list below:RAMROMPROMEEPROM Loading... 29. How many select lines will a 32 to 1 multiplexer will have4563 Loading... 30. The logic realized in the digital electronic circuit below is: F = A.CF = B.CF = A⊕CF = B⊕C Loading... 31. The simplest PLD isa MUXa NAND gatea flip-flopPAL Loading... 32. The greatest negative number which can be stored in an 8-bit computer using 2’s complement arithmetic is ________.-256-255-128-127 Loading... 33. The address inputs and data outputs of a 16K x 14 memory chip are ______.12, 1414, 1416, 1414, 12 Loading... 34. A PLA can be usedas a microprocessoras a dynamic memoryto realize sequential logicto realize combinational logic Loading... 35. Synchronous counters are slower than ripple counters.TrueFalse Loading... 36. The circuit shown below is _________. JK flip-flopJK flip-flop in Master-Slave configurationRS latchJohnson counter Loading... 37. In any Master-Slave configuration of flip-flops (D/T/JK/SR)Change in the input is immediately reflected in the outputChange in the output occurs when the state of the Master is affectedChange in the output occurs when the state of the Slave is affectedBoth the Master and Slave are affected at the same time Loading... 38. We use a dual-slope ADC in a digital voltmeter becauseIts accuracy is highIts conversion time is smallIt gives output in BCD formatIt does not require a comparator Loading... 39. How many types of digital comparators exist?1234 Loading... 40. The decimal number 10 is represented in its BCD form as _______.00010000001010111010000010100011 Loading...

Loading... 1. How many flip-flops are required to make a MOD-32 binary counter?35645 Loading... 2. A MOD-16 ripple counter is holding the count 1001_{2}. What will the count be after 31 clock pulses?1000100110101011 Loading... 3. The circuit shown below is a _______. Ring counterDecade counterPIPO shift registerPISO shift register Loading... 4. Two cascaded decade counters will divide the input frequency by ________.10100100020 Loading... 5. Any divide-by-N counter can be formed by using external gating to ________ at a predetermined number.ResetLOWPresetHIGH Loading... 6. The final count of a modulus-11 binary counter is ________.1000110010101011 Loading... 7. When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.ReciprocalLogProductExponent Loading... 8. A BCD counter is a ________.divide-by-10 counterDecade counterbinary counterfull-modulus counter Loading... 9. The flip-flops of a 4-bit ripple counter have a propagation delay from clock to Q output of 10 ns, each. For the counter to recycle from 1111 to 0000, it takes a total of ________.10ns30ns40ns45ns Loading... 10. Which of the following statements are true regarding a synchronous up/down counter?It can count in any direction but direction can't be changed once counting has startedThe direction can be changed midway, but the counter has to be reset before that can be doneThe counter can be reversed at any moment, no strings attachedThe direction cannot be changed midway, and when changed the counter has to be reset first Loading... 11. The delay problems encountered with asynchronous counters are removed with synchronous counters because the:input clock pulses are applied simultaneously to each stageinput clock pulses are not used to activate any of the counter stagesinput clock pulses are not used to activate any of the counter stagesinput clock pulses are applied only to the first and last stages Loading... 12. Which is not an example of a truncated modulus?981115 Loading... 13. _____ counter is a type of a shift register counter.BCDRingDecadeBinary Loading... 14. The resolution of an n bit DAC with a maximum input of 5 V is 5 mV. The value of n is …….10100111 Loading... 15. If A=B=D=0, and C=1, the value at OUT will be? LOWHIGHEither of the above, depending on the magnitudeZ Loading... 16. A ______ enables us to display a BCD code on a seven-segment display.EncoderDecoderMultiplexerDemultiplexer Loading... 17. If a BCD to seven-segment decoder sends 0111 to a seven-segment display, the segments that will go LOW are:a,b,cf,g,e,df,g,eall Loading... 18. _______ is the basic memory unit in digital electronics and hold 1-bit of data.EncoderNAND gateFlip-flopEXOR gate Loading... 19. We can use _______ and _______ to make a full addera half adder, an OR gatetwo half adders, an OR gatetwo half adders, two OR gatestwo half adders, two NOT gates Loading... 20. (7BF)_{16} = (?)_{2}1111 1011 10100111 1011 10100111 1011 10110111 1111 1010 Loading... 21. (?)_{8} = (E8)_{16}350250530333 Loading... 22. The decimal equivalent of the 2's complement of 11100101 is _________.0001101110011011+27-27 Loading... 23. Find Q AB + BC(B + C)AB + AC(B + C)BC + AB(B + C)AB + BC(A + B + C) Loading... 24. Select the Universal Logic gates from the following optionsNOTNANDNOREXNOR Loading... 25. Asynchronous circuits that change state immediately when enabled are called __________.Clock driven circuitsEvent driven circuitsPulse driven circuitsNone of these Loading... 26. We can erase the contents of an EPROM by exposing it to ________.MicrowavesUV raysInfrared raysGamma rays Loading... 27. This digital logic family has the lowest power dissipationTTLCMOSRTLDTL Loading... 28. Select the volatile memories from the list below:RAMROMPROMEEPROM Loading... 29. How many select lines will a 32 to 1 multiplexer will have4563 Loading... 30. The logic realized in the digital electronic circuit below is: F = A.CF = B.CF = A⊕CF = B⊕C Loading... 31. The simplest PLD isa MUXa NAND gatea flip-flopPAL Loading... 32. The greatest negative number which can be stored in an 8-bit computer using 2’s complement arithmetic is ________.-256-255-128-127 Loading... 33. The address inputs and data outputs of a 16K x 14 memory chip are ______.12, 1414, 1416, 1414, 12 Loading... 34. A PLA can be usedas a microprocessoras a dynamic memoryto realize sequential logicto realize combinational logic Loading... 35. Synchronous counters are slower than ripple counters.TrueFalse Loading... 36. The circuit shown below is _________. JK flip-flopJK flip-flop in Master-Slave configurationRS latchJohnson counter Loading... 37. In any Master-Slave configuration of flip-flops (D/T/JK/SR)Change in the input is immediately reflected in the outputChange in the output occurs when the state of the Master is affectedChange in the output occurs when the state of the Slave is affectedBoth the Master and Slave are affected at the same time Loading... 38. We use a dual-slope ADC in a digital voltmeter becauseIts accuracy is highIts conversion time is smallIt gives output in BCD formatIt does not require a comparator Loading... 39. How many types of digital comparators exist?1234 Loading... 40. The decimal number 10 is represented in its BCD form as _______.00010000001010111010000010100011 Loading...